[PATCH v2 04/10] usb: dwc3: core: Only handle soft-reset in DCTL

Eugen Hristev eugen.hristev at collabora.com
Tue Aug 1 09:28:05 CEST 2023

From: Venkatesh Yadav Abbarapu <venkatesh.abbarapu at amd.com>

[ Nguyen/Greg: Ported from Linux kernel commit
	f4fd84ae0765a ("usb: dwc3: core: Only handle soft-reset in DCTL") ]

Make sure not to set run_stop bit or link state change request while
initiating soft-reset. Register read-modify-write operation may
unintentionally start the controller before the initialization completes
with its previous DCTL value, which can cause initialization failure.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu at amd.com>
Not to be merged, I know Marek does not apply any patches to DWC3.

 drivers/usb/dwc3/core.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index bdfe51c3df96..06ca3fc96842 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -72,7 +72,8 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc)
 	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
-	dwc3_writel(dwc->regs, DWC3_DCTL, reg);
+	reg &= ~DWC3_DCTL_RUN_STOP;
+	dwc3_gadget_dctl_write_safe(dwc, reg);
 	/* Assert USB3 PHY reset */
 	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));

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