[PATCH v1 14/18] arm: rockchip: Add RK3588 arch core support

Kever Yang kever.yang at rock-chips.com
Thu Feb 16 09:57:25 CET 2023


Hi Jagan,

On 2023/1/30 22:57, Jagan Teki wrote:
> The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76
> and quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU,
> Mali-G610 MP4, HDMI Out, HDMI In, DP, eDP, MIPI DSI, MIPI CSI2,
> LPDDR4/4X/5, eMMC5.1, SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0,
> PCIe 3.0, SATA 3, Ethernet, SDIO3.0 I2C, UART, SPI, GPIO and PWM.
>
> Add arch core support for it.
>
> Signed-off-by: Jagan Teki <jagan at edgeble.ai>
> ---
>   arch/arm/include/asm/arch-rk3588/boot0.h      |  11 ++
>   arch/arm/include/asm/arch-rk3588/gpio.h       |  11 ++
>   arch/arm/mach-rockchip/Kconfig                |  20 +++
>   arch/arm/mach-rockchip/Makefile               |   1 +
>   arch/arm/mach-rockchip/rk3588/Kconfig         |  15 ++
>   arch/arm/mach-rockchip/rk3588/Makefile        |   9 +
>   arch/arm/mach-rockchip/rk3588/clk_rk3588.c    |  32 ++++
>   arch/arm/mach-rockchip/rk3588/rk3588.c        | 162 ++++++++++++++++++
>   arch/arm/mach-rockchip/rk3588/syscon_rk3588.c |  32 ++++
>   include/configs/rk3588_common.h               |  32 ++++
>   10 files changed, 325 insertions(+)
>   create mode 100644 arch/arm/include/asm/arch-rk3588/boot0.h
>   create mode 100644 arch/arm/include/asm/arch-rk3588/gpio.h
>   create mode 100644 arch/arm/mach-rockchip/rk3588/Kconfig
>   create mode 100644 arch/arm/mach-rockchip/rk3588/Makefile
>   create mode 100644 arch/arm/mach-rockchip/rk3588/clk_rk3588.c
>   create mode 100644 arch/arm/mach-rockchip/rk3588/rk3588.c
>   create mode 100644 arch/arm/mach-rockchip/rk3588/syscon_rk3588.c
>   create mode 100644 include/configs/rk3588_common.h
>
> diff --git a/arch/arm/include/asm/arch-rk3588/boot0.h b/arch/arm/include/asm/arch-rk3588/boot0.h
> new file mode 100644
> index 0000000000..dea2b20252
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rk3588/boot0.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * (C) Copyright 2021 Rockchip Electronics Co., Ltd
> + */
> +
> +#ifndef __ASM_ARCH_BOOT0_H__
> +#define __ASM_ARCH_BOOT0_H__
> +
> +#include <asm/arch-rockchip/boot0.h>
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-rk3588/gpio.h b/arch/arm/include/asm/arch-rk3588/gpio.h
> new file mode 100644
> index 0000000000..b48c0a5cf8
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rk3588/gpio.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * (C) Copyright 2021 Rockchip Electronics Co., Ltd
> + */
> +
> +#ifndef __ASM_ARCH_GPIO_H__
> +#define __ASM_ARCH_GPIO_H__
> +
> +#include <asm/arch-rockchip/gpio.h>
> +
> +#endif
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> index b678ec4131..71774a5f2e 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -294,6 +294,25 @@ config ROCKCHIP_RK3568
>   	  and video codec support. Peripherals include Gigabit Ethernet,
>   	  USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
>   
> +config ROCKCHIP_RK3588
> +	bool "Support Rockchip RK3588"
> +	select ARM64
> +	select SUPPORT_SPL
> +	select SPL
> +	select CLK
> +	select PINCTRL
> +	select RAM
> +	select REGMAP
> +	select SYSCON
> +	select BOARD_LATE_INIT
> +	imply ROCKCHIP_COMMON_BOARD
> +	help
> +	  The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and
> +	  quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4,
> +	  HDMI Out, HDMI In, DP, eDP, MIPI DSI, MIPI CSI2, LPDDR4/4X/5, eMMC5.1,
> +	  SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0, PCIe 3.0, SATA 3, Ethernet,
> +	  SDIO3.0 I2C, UART, SPI, GPIO and PWM.
> +
>   config ROCKCHIP_RV1108
>   	bool "Support Rockchip RV1108"
>   	select CPU_V7A
> @@ -491,6 +510,7 @@ source "arch/arm/mach-rockchip/rk3328/Kconfig"
>   source "arch/arm/mach-rockchip/rk3368/Kconfig"
>   source "arch/arm/mach-rockchip/rk3399/Kconfig"
>   source "arch/arm/mach-rockchip/rk3568/Kconfig"
> +source "arch/arm/mach-rockchip/rk3588/Kconfig"
>   source "arch/arm/mach-rockchip/rv1108/Kconfig"
>   source "arch/arm/mach-rockchip/rv1126/Kconfig"
>   endif
> diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
> index 32138fa723..bee4fa4b5a 100644
> --- a/arch/arm/mach-rockchip/Makefile
> +++ b/arch/arm/mach-rockchip/Makefile
> @@ -44,6 +44,7 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
>   obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
>   obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
>   obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/
> +obj-$(CONFIG_ROCKCHIP_RK3588) += rk3588/
>   obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
>   obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/
>   
> diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig
> new file mode 100644
> index 0000000000..e8c14e4187
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3588/Kconfig
> @@ -0,0 +1,15 @@
> +if ROCKCHIP_RK3588
> +
> +config ROCKCHIP_BOOT_MODE_REG
> +	default 0xfd588080
> +
> +config ROCKCHIP_STIMER_BASE
> +	default 0xfd8c8000
> +
> +config SYS_SOC
> +	default "rk3588"
> +
> +config SYS_MALLOC_F_LEN
> +	default 0x80000
> +
> +endif
> diff --git a/arch/arm/mach-rockchip/rk3588/Makefile b/arch/arm/mach-rockchip/rk3588/Makefile
> new file mode 100644
> index 0000000000..4003eea87a
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3588/Makefile
> @@ -0,0 +1,9 @@
> +#
> +# (C) Copyright 2021 Rockchip Electronics Co., Ltd
> +#
> +# SPDX-License-Identifier:     GPL-2.0+
> +#
> +
> +obj-y += rk3588.o
> +obj-y += clk_rk3588.o
> +obj-y += syscon_rk3588.o
> diff --git a/arch/arm/mach-rockchip/rk3588/clk_rk3588.c b/arch/arm/mach-rockchip/rk3588/clk_rk3588.c
> new file mode 100644
> index 0000000000..3df0bf223e
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3588/clk_rk3588.c
> @@ -0,0 +1,32 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * (C) Copyright 2020 Rockchip Electronics Co., Ltd.
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <syscon.h>
> +#include <asm/arch-rockchip/clock.h>
> +#include <asm/arch-rockchip/cru_rk3588.h>
> +#include <linux/err.h>
> +
> +int rockchip_get_clk(struct udevice **devp)
> +{
> +	return uclass_get_device_by_driver(UCLASS_CLK,
> +			DM_DRIVER_GET(rockchip_rk3588_cru), devp);
> +}
> +
> +void *rockchip_get_cru(void)
> +{
> +	struct rk3588_clk_priv *priv;
> +	struct udevice *dev;
> +	int ret;
> +
> +	ret = rockchip_get_clk(&dev);
> +	if (ret)
> +		return ERR_PTR(ret);
> +
> +	priv = dev_get_priv(dev);
> +
> +	return priv->cru;
> +}
> diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c
> new file mode 100644
> index 0000000000..8e4f5e55f4
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
> @@ -0,0 +1,162 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2021 Rockchip Electronics Co., Ltd
> + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
> + */
> +
> +#include <common.h>
> +#include <spl.h>
> +#include <asm/armv8/mmu.h>
> +#include <asm/io.h>
> +#include <asm/arch-rockchip/hardware.h>
> +#include <asm/arch-rockchip/ioc_rk3588.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define FIREWALL_DDR_BASE		0xfe030000
> +#define FW_DDR_MST5_REG			0x54
> +#define FW_DDR_MST13_REG		0x74
> +#define FW_DDR_MST21_REG		0x94
> +#define FW_DDR_MST26_REG		0xa8
> +#define FW_DDR_MST27_REG		0xac
> +#define FIREWALL_SYSMEM_BASE		0xfe038000
> +#define FW_SYSM_MST5_REG		0x54
> +#define FW_SYSM_MST13_REG		0x74
> +#define FW_SYSM_MST21_REG		0x94
> +#define FW_SYSM_MST26_REG		0xa8
> +#define FW_SYSM_MST27_REG		0xac
> +
> +#define PMU1_IOC_BASE			0xfd5f0000
> +#define PMU2_IOC_BASE			0xfd5f4000
> +
> +#define BUS_IOC_BASE			0xfd5f8000
> +#define BUS_IOC_GPIO2A_IOMUX_SEL_L	0x40
> +#define BUS_IOC_GPIO2B_IOMUX_SEL_L	0x48
> +#define BUS_IOC_GPIO2D_IOMUX_SEL_L	0x58
> +#define BUS_IOC_GPIO2D_IOMUX_SEL_H	0x5c
> +#define BUS_IOC_GPIO3A_IOMUX_SEL_L	0x60
> +
> +static struct mm_region rk3588_mem_map[] = {
> +	{
> +		.virt = 0x0UL,
> +		.phys = 0x0UL,
> +		.size = 0xf0000000UL,
> +		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> +			 PTE_BLOCK_INNER_SHARE
> +	}, {
> +		.virt = 0xf0000000UL,
> +		.phys = 0xf0000000UL,
> +		.size = 0x10000000UL,
> +		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> +			 PTE_BLOCK_NON_SHARE |
> +			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
> +	},  {
> +		.virt = 0x900000000,
> +		.phys = 0x900000000,
> +		.size = 0x150000000,
> +		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> +			 PTE_BLOCK_NON_SHARE |
> +			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
> +	},  {
> +		/* List terminator */
> +		0,
> +	}
> +};
> +
> +struct mm_region *mem_map = rk3588_mem_map;
> +
> +/* GPIO0B_IOMUX_SEL_H */
> +enum {
> +	GPIO0B5_SHIFT		= 4,
> +	GPIO0B5_MASK		= GENMASK(7, 4),
> +	GPIO0B5_REFER		= 8,
> +	GPIO0B5_UART2_TX_M0	= 10,
> +
> +	GPIO0B6_SHIFT		= 8,
> +	GPIO0B6_MASK		= GENMASK(11, 8),
> +	GPIO0B6_REFER		= 8,
> +	GPIO0B6_UART2_RX_M0	= 10,
> +};
> +
> +void board_debug_uart_init(void)
> +{
> +	__maybe_unused static struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE;
> +	static struct rk3588_pmu2_ioc * const pmu2_ioc = (void *)PMU2_IOC_BASE;
> +
> +	/* Refer to BUS_IOC */
> +	rk_clrsetreg(&pmu2_ioc->gpio0b_iomux_sel_h,
> +		     GPIO0B6_MASK | GPIO0B5_MASK,
> +		     GPIO0B6_REFER << GPIO0B6_SHIFT |
> +		     GPIO0B5_REFER << GPIO0B5_SHIFT);
> +
> +	/* UART2_M0 Switch iomux */
> +	rk_clrsetreg(&bus_ioc->gpio0b_iomux_sel_h,
> +		     GPIO0B6_MASK | GPIO0B5_MASK,
> +		     GPIO0B6_UART2_RX_M0 << GPIO0B6_SHIFT |
> +		     GPIO0B5_UART2_TX_M0 << GPIO0B5_SHIFT);
> +}
> +
> +#ifdef CONFIG_SPL_BUILD
> +void rockchip_stimer_init(void)
> +{
> +	/* If Timer already enabled, don't re-init it */
> +	u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
> +
> +	if (reg & 0x1)
> +		return;
> +
> +	asm volatile("msr CNTFRQ_EL0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY));
> +	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
> +	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
> +	writel(0x1, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
> +}
> +#endif
> +
> +#ifndef CONFIG_TPL_BUILD
> +int arch_cpu_init(void)
> +{
> +#ifdef CONFIG_SPL_BUILD
> +	int secure_reg;
> +
> +	/* Set the SDMMC eMMC crypto_ns FSPI access secure area */
> +	secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
> +	secure_reg &= 0xffff;
> +	writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
> +	secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
> +	secure_reg &= 0xffff;
> +	writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
> +	secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
> +	secure_reg &= 0xffff;
> +	writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
> +	secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
> +	secure_reg &= 0xffff;
> +	writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
> +	secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
> +	secure_reg &= 0xffff0000;
> +	writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
> +
> +	secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
> +	secure_reg &= 0xffff;
> +	writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
> +	secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
> +	secure_reg &= 0xffff;
> +	writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
> +	secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
> +	secure_reg &= 0xffff;
> +	writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
> +	secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
> +	secure_reg &= 0xffff;
> +	writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
> +	secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
> +	secure_reg &= 0xffff0000;
> +	writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
> +
> +	/* Set emmc iomux for good extension if the emmc is not the boot device */
> +	writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2A_IOMUX_SEL_L);
> +	writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L);
> +	writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_H);

This patch is modify from rockchip vendor U-Boot, please don't make the 
emmc iomux default

  as other function because rk3588-evb1 does use it.

Other parts looks good to me.


Thanks,

- Kever

> +#endif
> +
> +	return 0;
> +}
> +#endif
> diff --git a/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c b/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c
> new file mode 100644
> index 0000000000..e8772d3a38
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c
> @@ -0,0 +1,32 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2021 Rockchip Electronics Co., Ltd
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <syscon.h>
> +#include <asm/arch-rockchip/clock.h>
> +
> +static const struct udevice_id rk3588_syscon_ids[] = {
> +	{ .compatible = "rockchip,rk3588-sys-grf", .data = ROCKCHIP_SYSCON_GRF },
> +	{ .compatible = "rockchip,rk3588-pmu1-grf", .data = ROCKCHIP_SYSCON_PMUGRF },
> +	{ .compatible = "rockchip,rk3588-vop-grf", .data = ROCKCHIP_SYSCON_VOP_GRF },
> +	{ .compatible = "rockchip,rk3588-vo-grf",  .data = ROCKCHIP_SYSCON_VO_GRF },
> +	{ .compatible = "rockchip,pcie30-phy-grf", .data = ROCKCHIP_SYSCON_PCIE30_PHY_GRF },
> +	{ .compatible = "rockchip,rk3588-php-grf", .data = ROCKCHIP_SYSCON_PHP_GRF },
> +	{ .compatible = "rockchip,pipe-phy-grf",   .data = ROCKCHIP_SYSCON_PIPE_PHY0_GRF },
> +	{ .compatible = "rockchip,pipe-phy-grf",   .data = ROCKCHIP_SYSCON_PIPE_PHY1_GRF },
> +	{ .compatible = "rockchip,pipe-phy-grf",   .data = ROCKCHIP_SYSCON_PIPE_PHY2_GRF },
> +	{ .compatible = "rockchip,rk3588-pmu",     .data = ROCKCHIP_SYSCON_PMU },
> +	{ }
> +};
> +
> +U_BOOT_DRIVER(syscon_rk3588) = {
> +	.name = "rk3588_syscon",
> +	.id = UCLASS_SYSCON,
> +	.of_match = rk3588_syscon_ids,
> +#if CONFIG_IS_ENABLED(OF_REAL)
> +	.bind = dm_scan_fdt_dev,
> +#endif
> +};
> diff --git a/include/configs/rk3588_common.h b/include/configs/rk3588_common.h
> new file mode 100644
> index 0000000000..abd20139aa
> --- /dev/null
> +++ b/include/configs/rk3588_common.h
> @@ -0,0 +1,32 @@
> +/* SPDX-License-Identifier:     GPL-2.0+ */
> +/*
> + * (C) Copyright 2021 Rockchip Electronics Co., Ltd
> + * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
> + */
> +
> +#ifndef __CONFIG_RK3588_COMMON_H
> +#define __CONFIG_RK3588_COMMON_H
> +
> +#include "rockchip-common.h"
> +
> +#define CFG_IRAM_BASE			0xff000000
> +
> +#define CFG_SYS_SDRAM_BASE		0
> +#define SDRAM_MAX_SIZE			0xf0000000
> +
> +#define ENV_MEM_LAYOUT_SETTINGS		\
> +	"scriptaddr=0x00c00000\0"	\
> +	"pxefile_addr_r=0x00e00000\0"	\
> +	"fdt_addr_r=0x0a100000\0"	\
> +	"kernel_addr_r=0x02080000\0"	\
> +	"ramdisk_addr_r=0x0a200000\0"
> +
> +#include <config_distro_bootcmd.h>
> +#define CFG_EXTRA_ENV_SETTINGS \
> +	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
> +	"partitions=" PARTS_DEFAULT		\
> +	ENV_MEM_LAYOUT_SETTINGS			\
> +	ROCKCHIP_DEVICE_SETTINGS		\
> +	BOOTENV
> +
> +#endif /* __CONFIG_RK3588_COMMON_H */


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