[PATCH v2 00/17] Basic StarFive JH7110 RISC-V SoC support
yanhong wang
yanhong.wang at starfivetech.com
Thu Feb 16 10:01:52 CET 2023
On 2023/1/24 8:28, Heinrich Schuchardt wrote:
>
>
> On 1/18/23 09:11, Yanhong Wang wrote:
>> This series of patches base on the latest branch/master, and add support
>> for the StarFive JH7110 RISC-V SoC and VisionFive V2 board. In order for
>> this to be achieved, the respective DT nodes have been added, and the
>> required defconfigs have been added to the boards' defconfig. What is more,
>> the basic required DM drivers have been added, such as reset, clock, pinctrl,
>> uart, ram etc.
>>
>> Note that the register base address of reset controller is same with the
>> clock controller. Therefore, there is no device tree node alone for reset
>> driver. It binds device node in the clock driver.
>>
>> The u-boot-spl and u-boot has been tested on the VisionFive V2 boards which
>> equip with JH7110 SoC and works normally.
>>
>> For more information and support, you can visit RVspace wiki[1].
>
> Hello Yanhong,
>
> Which version of OpenSBI is needed for this series to work?
>
> Could you, please, provide a file in doc/board/starfive/ describing how to build and install U-Boot on the board.
>
> Is tool create_sbl from https://github.com/starfive-tech/Tools still required? Can the source code for that tool be made available? Ideally this would be integrated into binman.
>
> This is what I have in my notes:
>
> cd Tools && \
> ./create_sbl $(uboot_wrkdir)/spl/u-boot-spl.bin 0x01010101
>
Thanks. Yes, u-boot-spl.bin also need to be converted by the create_sbl tool.
The source code of the tool has been available. View details [1]
I will add doc/board/starfive/visionfive2.rst to describe how to build and install u-boot on the board in the next version.
[1] https://github.com/starfive-tech/Tools/tree/master/spl_tool
> Best regards
>
> Heinrich
>
>>
>> [1] https://wiki.rvspace.org/
>>
>> Changes in v2:
>> - Renamed file 'jh7110-regs.h' to 'regs.h'.
>> - Reworded the clear L2 LIM memory code in C.
>> - Removed flash init call in 'spl_soc_init' function.
>> - Reworded the clock driver.
>> - Rename the macro 'SET_DIV' to 'ASSIGNED_CLOCK_PARENTS' in 'spl.c'.
>> - Moved the device tree node 'dmc at 15700000' from 'jh7110-u-boot.dtsi' to
>> 'starfive_visionfive2-u-boot.dtsi'.
>>
>> Previous versions:
>> v1 - https://patchwork.ozlabs.org/project/uboot/cover/20221212025020.23778-1-yanhong.wang@starfivetech.com/
>>
>> Jianlong Huang (1):
>> dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions
>>
>> Kuan Lim Lee (1):
>> pinctrl: starfive: Add StarFive JH7110 driver
>>
>> Yanhong Wang (15):
>> riscv: cpu: jh7110: Add support for jh7110 SoC
>> cache: starfive: Add StarFive JH7110 support
>> dt-bindings: reset: Add StarFive JH7110 reset definitions
>> reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoC
>> dt-bindings: clock: Add StarFive JH7110 clock definitions
>> clk: starfive: Add StarFive JH7110 clock driver
>> ram: starfive: add ddr driver
>> board: starfive: add StarFive VisionFive v2 board support
>> riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC
>> board: starfive: Add Kconfig for StarFive VisionFive v2 Board
>> board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig
>> riscv: dts: jh7110: Add initial StarFive JH7110 device tree
>> riscv: dts: jh7110: Add initial u-boot device tree
>> riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device
>> tree
>> configs: starfive: add starfive_visionfive2_defconfig
>>
>> arch/riscv/Kconfig | 5 +
>> arch/riscv/cpu/jh7110/Kconfig | 28 +
>> arch/riscv/cpu/jh7110/Makefile | 10 +
>> arch/riscv/cpu/jh7110/cpu.c | 23 +
>> arch/riscv/cpu/jh7110/dram.c | 38 +
>> arch/riscv/cpu/jh7110/spl.c | 64 +
>> arch/riscv/dts/Makefile | 2 +-
>> arch/riscv/dts/jh7110-u-boot.dtsi | 72 +
>> arch/riscv/dts/jh7110.dtsi | 497 +++++
>> .../dts/starfive_visionfive2-u-boot.dtsi | 84 +
>> arch/riscv/dts/starfive_visionfive2.dts | 234 ++
>> arch/riscv/include/asm/arch-jh7110/regs.h | 19 +
>> arch/riscv/include/asm/arch-jh7110/spl.h | 12 +
>> board/starfive/visionfive2/Kconfig | 53 +
>> board/starfive/visionfive2/MAINTAINERS | 7 +
>> board/starfive/visionfive2/Makefile | 7 +
>> board/starfive/visionfive2/spl.c | 118 +
>> .../visionfive2/starfive_visionfive2.c | 38 +
>> configs/starfive_visionfive2_defconfig | 72 +
>> drivers/cache/cache-sifive-ccache.c | 1 +
>> drivers/clk/Kconfig | 1 +
>> drivers/clk/Makefile | 1 +
>> drivers/clk/starfive/Kconfig | 17 +
>> drivers/clk/starfive/Makefile | 4 +
>> drivers/clk/starfive/clk-jh7110-pll.c | 293 +++
>> drivers/clk/starfive/clk-jh7110.c | 559 +++++
>> drivers/clk/starfive/clk.h | 60 +
>> drivers/pinctrl/Kconfig | 1 +
>> drivers/pinctrl/Makefile | 1 +
>> drivers/pinctrl/starfive/Kconfig | 16 +
>> drivers/pinctrl/starfive/Makefile | 6 +
>> drivers/pinctrl/starfive/pinctrl-jh7110-aon.c | 113 +
>> drivers/pinctrl/starfive/pinctrl-jh7110-sys.c | 399 ++++
>> drivers/pinctrl/starfive/pinctrl-starfive.c | 428 ++++
>> drivers/pinctrl/starfive/pinctrl-starfive.h | 55 +
>> drivers/ram/Kconfig | 1 +
>> drivers/ram/Makefile | 4 +-
>> drivers/ram/starfive/Kconfig | 5 +
>> drivers/ram/starfive/Makefile | 11 +
>> drivers/ram/starfive/ddrcsr_boot.c | 339 +++
>> drivers/ram/starfive/ddrphy_start.c | 279 +++
>> drivers/ram/starfive/ddrphy_train.c | 383 ++++
>> drivers/ram/starfive/ddrphy_utils.c | 1955 +++++++++++++++++
>> drivers/ram/starfive/starfive_ddr.c | 161 ++
>> drivers/ram/starfive/starfive_ddr.h | 65 +
>> drivers/reset/Kconfig | 16 +
>> drivers/reset/Makefile | 1 +
>> drivers/reset/reset-jh7110.c | 158 ++
>> include/configs/starfive-visionfive2.h | 18 +
>> include/dt-bindings/clock/starfive-jh7110.h | 271 +++
>> .../pinctrl/pinctrl-starfive-jh7110.h | 427 ++++
>> include/dt-bindings/reset/starfive-jh7110.h | 183 ++
>> 52 files changed, 7613 insertions(+), 2 deletions(-)
>> create mode 100644 arch/riscv/cpu/jh7110/Kconfig
>> create mode 100644 arch/riscv/cpu/jh7110/Makefile
>> create mode 100644 arch/riscv/cpu/jh7110/cpu.c
>> create mode 100644 arch/riscv/cpu/jh7110/dram.c
>> create mode 100644 arch/riscv/cpu/jh7110/spl.c
>> create mode 100644 arch/riscv/dts/jh7110-u-boot.dtsi
>> create mode 100644 arch/riscv/dts/jh7110.dtsi
>> create mode 100644 arch/riscv/dts/starfive_visionfive2-u-boot.dtsi
>> create mode 100644 arch/riscv/dts/starfive_visionfive2.dts
>> create mode 100644 arch/riscv/include/asm/arch-jh7110/regs.h
>> create mode 100644 arch/riscv/include/asm/arch-jh7110/spl.h
>> create mode 100644 board/starfive/visionfive2/Kconfig
>> create mode 100644 board/starfive/visionfive2/MAINTAINERS
>> create mode 100644 board/starfive/visionfive2/Makefile
>> create mode 100644 board/starfive/visionfive2/spl.c
>> create mode 100644 board/starfive/visionfive2/starfive_visionfive2.c
>> create mode 100644 configs/starfive_visionfive2_defconfig
>> create mode 100644 drivers/clk/starfive/Kconfig
>> create mode 100644 drivers/clk/starfive/Makefile
>> create mode 100644 drivers/clk/starfive/clk-jh7110-pll.c
>> create mode 100644 drivers/clk/starfive/clk-jh7110.c
>> create mode 100644 drivers/clk/starfive/clk.h
>> create mode 100644 drivers/pinctrl/starfive/Kconfig
>> create mode 100644 drivers/pinctrl/starfive/Makefile
>> create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-aon.c
>> create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
>> create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.c
>> create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.h
>> create mode 100644 drivers/ram/starfive/Kconfig
>> create mode 100644 drivers/ram/starfive/Makefile
>> create mode 100644 drivers/ram/starfive/ddrcsr_boot.c
>> create mode 100644 drivers/ram/starfive/ddrphy_start.c
>> create mode 100644 drivers/ram/starfive/ddrphy_train.c
>> create mode 100644 drivers/ram/starfive/ddrphy_utils.c
>> create mode 100644 drivers/ram/starfive/starfive_ddr.c
>> create mode 100644 drivers/ram/starfive/starfive_ddr.h
>> create mode 100644 drivers/reset/reset-jh7110.c
>> create mode 100644 include/configs/starfive-visionfive2.h
>> create mode 100644 include/dt-bindings/clock/starfive-jh7110.h
>> create mode 100644 include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h
>> create mode 100644 include/dt-bindings/reset/starfive-jh7110.h
>>
>>
>> base-commit: 348064ee2c8f9494b91b55729ac60c5db79ef129
>> Tested-by: Conor Dooley <conor.dooley at microchip.com>
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