[PATCH v2 00/17] Basic StarFive JH7110 RISC-V SoC support

[yanhong wang]

On 2023/1/22 5:56, Sean Anderson wrote:
> On 1/21/23 16:36, Conor Dooley wrote:
>> On Wed, Jan 18, 2023 at 04:11:15PM +0800, Yanhong Wang wrote:
>>> This series of patches base on the latest branch/master, and add support
>>> for the StarFive JH7110 RISC-V SoC and VisionFive V2 board. In order for
>>> this to be achieved, the respective DT nodes have been added,  and the
>>> required defconfigs have been added to the boards' defconfig. What is more,
>>> the basic required DM drivers have been added, such as reset, clock, pinctrl,
>>> uart, ram etc.
>>>
>>> Note that the register base address of reset controller is same with the
>>> clock controller. Therefore, there is no device tree node alone for reset
>>> driver. It binds device node in the clock driver.
>>>
>>> The u-boot-spl and u-boot has been tested on the VisionFive V2 boards which
>>> equip with JH7110 SoC and works normally.
>>>
>>> For more information and support, you can visit RVspace wiki[1].
>>>
>>> [1] https://wiki.rvspace.org/
>>>
>>> Changes in v2:
>>> - Renamed file 'jh7110-regs.h' to 'regs.h'.
>>> - Reworded the clear L2 LIM memory code in C.
>>> - Removed flash init call in 'spl_soc_init' function.
>>> - Reworded the clock driver.
>>> - Rename the macro 'SET_DIV' to 'ASSIGNED_CLOCK_PARENTS' in 'spl.c'.
>>> - Moved the device tree node 'dmc at 15700000' from 'jh7110-u-boot.dtsi' to
>>>    'starfive_visionfive2-u-boot.dtsi'.
>>>
>>> Previous versions:
>>> v1 - https://patchwork.ozlabs.org/project/uboot/cover/20221212025020.23778-1-yanhong.wang@starfivetech.com/
>>>
>>> Jianlong Huang (1):
>>>    dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions
>>>
>>> Kuan Lim Lee (1):
>>>    pinctrl: starfive: Add StarFive JH7110 driver
>>>
>>> Yanhong Wang (15):
>>>    riscv: cpu: jh7110: Add support for jh7110 SoC
>>>    cache: starfive: Add StarFive JH7110 support
>>>    dt-bindings: reset: Add StarFive JH7110 reset definitions
>>>    reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoC
>>>    dt-bindings: clock: Add StarFive JH7110 clock definitions
>>>    clk: starfive: Add StarFive JH7110 clock driver
>>>    ram: starfive: add ddr driver
>>>    board: starfive: add StarFive VisionFive v2 board support
>>>    riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC
>>>    board: starfive: Add Kconfig for StarFive VisionFive v2 Board
>>>    board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig
>>>    riscv: dts: jh7110: Add initial StarFive JH7110 device tree
>>>    riscv: dts: jh7110: Add initial u-boot device tree
>>>    riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device
>>>      tree
>>>    configs: starfive: add starfive_visionfive2_defconfig
>>
>> Apologies if I have missed it somewhere - but where is patch 12?
>> I don't see it on lore.kernel.org nor in my inbox :(
>>
>> Thanks,
>> Conor.
>>
> 
> https://lore.kernel.org/all/20230118082907.31629-1-yanhong.wang@starfivetech.com/
> 
> Not sure why it isn't with the rest of the series.
> 

It was reported send fail when sending patch 12, so it was sent separately later

> --Sean