[PATCH V4 0/2] spi: cqspi: Fix register reads in STIG Mode

[Dhruva Gole]

Intent of these patches is to fix register reads in STIG mode and also
use STIG mode while reading flash registers.
Currently if you try to read a register while in STIG mode there is no
support for ADDR and thus naturally a register never gets read from the
flash.

This series supercedes the previously sent:
https://lore.kernel.org/u-boot/20221125055932.398322-1-d-gole@ti.com/

Logs demonstrating the usage and working of QSPI-NOR Flash (Cypress
s25hs512t) can be found on the link below:
https://gist.github.com/DhruvaG2000/11e7b4ee6a381be9d86b69b2bc2616e4

change log:
----------

v4:
* Improve the commit message for PATCH 2/2
* Address Pratyush's review to use <= CQSPI_STIG_DATA_LEN_MAX instead.

v3: Improvements over the last 2 versions, I have added a bit mask to
make sure nbytes dont overflow bit fields. Also minor improvements in
wording of comments and commit log.

v2: add the setup ADDR bits patch because STIG read of registers wasn't
present earlier.

v1: use STIG mode if reads are small.


Dhruva Gole (2):
  spi: cadence_qspi: setup ADDR Bits in cmd reads
  spi: cadence_qspi: use STIG mode for small reads

 drivers/spi/cadence_qspi.c     |  8 +++++++-
 drivers/spi/cadence_qspi_apb.c | 13 +++++++++++++
 2 files changed, 20 insertions(+), 1 deletion(-)

-- 
2.25.1