[PATCH 3/3] clk: imx8mn: fix imx8mn_enet_phy_sels clocks list
Sean Anderson
seanga2 at gmail.com
Wed Jan 4 18:27:40 CET 2023
On 12/19/22 06:31, Dario Binacchi wrote:
> [backport from linux commit 2626cf67f20b28446dfc3a5b9493dd535cdb747b]
>
> According to the "Clock Root" table of the reference manual (document
> IMX8MNRM Rev 2, 07/2022):
>
> Clock Root offset Source Select (CCM_TARGET_ROOTn[MUX])
> ... ... ...
> ENET_PHY_REF_CLK_ROOT 0xAA80 000 - 24M_REF_CLK
> 001 - SYSTEM_PLL2_DIV20
> 010 - SYSTEM_PLL2_DIV8
> 011 - SYSTEM_PLL2_DIV5
> 100 - SYSTEM_PLL2_DIV2
> 101 - AUDIO_PLL1_CLK
> 110 - VIDEO_PLL_CLK
> 111 - AUDIO_PLL2_CLK
> ... ... ...
>
> while the imx8mn_enet_phy_sels list didn't contained audio_pll1_out for
> source select bits 101b.
>
> Signed-off-by: Dario Binacchi <dario.binacchi at amarulasolutions.com>
>
> ---
>
> drivers/clk/imx/clk-imx8mn.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
> index a2c7c63ef74d..692823e74b88 100644
> --- a/drivers/clk/imx/clk-imx8mn.c
> +++ b/drivers/clk/imx/clk-imx8mn.c
> @@ -41,7 +41,7 @@ static const char *imx8mn_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m",
> "clk_ext3", "clk_ext4", "video_pll_out", };
>
> static const char *imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
> - "sys_pll2_500m", "video_pll_out", "audio_pll2_out", };
> + "sys_pll2_500m", "audio_pll1_out", "video_pll_out", "audio_pll2_out", };
> #endif
>
> static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
Acked-by: Sean Anderson <seanga2 at gmail.com>
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