[PATCH v1 03/16] ARM: tegra: clock: add clk_id_to_pll_id helper
Svyatoslav Ryhel
clamor95 at gmail.com
Sun Jan 29 19:41:10 CET 2023
This function allows to convert a device tree clock ID to PLL ID.
Tested-by: Andreas Westman Dorcsak <hedmoo at yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob at gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95 at gmail.com> # HTC One X
Signed-off-by: Svyatoslav Ryhel <clamor95 at gmail.com>
---
arch/arm/include/asm/arch-tegra/clock.h | 8 ++++++
arch/arm/mach-tegra/tegra114/clock.c | 37 ++++++++++++++++++++++++
arch/arm/mach-tegra/tegra124/clock.c | 38 +++++++++++++++++++++++++
arch/arm/mach-tegra/tegra20/clock.c | 37 ++++++++++++++++++++++++
arch/arm/mach-tegra/tegra210/clock.c | 37 ++++++++++++++++++++++++
arch/arm/mach-tegra/tegra30/clock.c | 37 ++++++++++++++++++++++++
6 files changed, 194 insertions(+)
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index 6586015fd2..05b3bc2122 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -353,6 +353,14 @@ int get_periph_clock_source(enum periph_id periph_id,
*/
enum periph_id clk_id_to_periph_id(int clk_id);
+/*
+ * Convert a device tree clock ID to our PLL ID.
+ *
+ * @param clk_id Clock ID according to tegra device tree binding
+ * Return: clock ID, or CLOCK_ID_NONE if the clock ID is invalid
+ */
+enum clock_id clk_id_to_pll_id(int clk_id);
+
/**
* Set the output frequency you want for each PLL clock.
* PLL output frequencies are programmed by setting their N, M and P values.
diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c
index 703a2314e7..fb9780f826 100644
--- a/arch/arm/mach-tegra/tegra114/clock.c
+++ b/arch/arm/mach-tegra/tegra114/clock.c
@@ -19,6 +19,8 @@
#include <fdtdec.h>
#include <linux/delay.h>
+#include <dt-bindings/clock/tegra114-car.h>
+
/*
* Clock types that we can use as a source. The Tegra114 has muxes for the
* peripheral clocks, and in most cases there are four options for the clock
@@ -652,6 +654,41 @@ enum periph_id clk_id_to_periph_id(int clk_id)
return clk_id;
}
}
+
+/*
+ * Convert a device tree clock ID to our PLL ID.
+ *
+ * @param clk_id Clock ID according to tegra114 device tree binding
+ * Return: clock ID, or CLOCK_ID_NONE if the clock ID is invalid
+ */
+enum clock_id clk_id_to_pll_id(int clk_id)
+{
+ switch (clk_id) {
+ case TEGRA114_CLK_PLL_C:
+ return CLOCK_ID_CGENERAL;
+ case TEGRA114_CLK_PLL_M:
+ return CLOCK_ID_MEMORY;
+ case TEGRA114_CLK_PLL_P:
+ return CLOCK_ID_PERIPH;
+ case TEGRA114_CLK_PLL_A:
+ return CLOCK_ID_AUDIO;
+ case TEGRA114_CLK_PLL_U:
+ return CLOCK_ID_USB;
+ case TEGRA114_CLK_PLL_D:
+ case TEGRA114_CLK_PLL_D_OUT0:
+ return CLOCK_ID_DISPLAY;
+ case TEGRA114_CLK_PLL_X:
+ return CLOCK_ID_XCPU;
+ case TEGRA114_CLK_PLL_E:
+ return CLOCK_ID_EPCI;
+ case TEGRA114_CLK_CLK_32K:
+ return CLOCK_ID_32KHZ;
+ case TEGRA114_CLK_CLK_M:
+ return CLOCK_ID_CLK_M;
+ default:
+ return CLOCK_ID_NONE;
+ }
+}
#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
void clock_early_init(void)
diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c
index bbfe184652..ffa5437630 100644
--- a/arch/arm/mach-tegra/tegra124/clock.c
+++ b/arch/arm/mach-tegra/tegra124/clock.c
@@ -19,6 +19,9 @@
#include <fdtdec.h>
#include <linux/delay.h>
+#include <dt-bindings/clock/tegra124-car.h>
+#include <dt-bindings/clock/tegra124-car-common.h>
+
/*
* Clock types that we can use as a source. The Tegra124 has muxes for the
* peripheral clocks, and in most cases there are four options for the clock
@@ -832,6 +835,41 @@ enum periph_id clk_id_to_periph_id(int clk_id)
return clk_id;
}
}
+
+/*
+ * Convert a device tree clock ID to our PLL ID.
+ *
+ * @param clk_id Clock ID according to tegra124 device tree binding
+ * Return: clock ID, or CLOCK_ID_NONE if the clock ID is invalid
+ */
+enum clock_id clk_id_to_pll_id(int clk_id)
+{
+ switch (clk_id) {
+ case TEGRA124_CLK_PLL_C:
+ return CLOCK_ID_CGENERAL;
+ case TEGRA124_CLK_PLL_M:
+ return CLOCK_ID_MEMORY;
+ case TEGRA124_CLK_PLL_P:
+ return CLOCK_ID_PERIPH;
+ case TEGRA124_CLK_PLL_A:
+ return CLOCK_ID_AUDIO;
+ case TEGRA124_CLK_PLL_U:
+ return CLOCK_ID_USB;
+ case TEGRA124_CLK_PLL_D:
+ case TEGRA124_CLK_PLL_D_OUT0:
+ return CLOCK_ID_DISPLAY;
+ case TEGRA124_CLK_PLL_X:
+ return CLOCK_ID_XCPU;
+ case TEGRA124_CLK_PLL_E:
+ return CLOCK_ID_EPCI;
+ case TEGRA124_CLK_CLK_32K:
+ return CLOCK_ID_32KHZ;
+ case TEGRA124_CLK_CLK_M:
+ return CLOCK_ID_CLK_M;
+ default:
+ return CLOCK_ID_NONE;
+ }
+}
#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
void clock_early_init(void)
diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c
index 755167e068..279b21f841 100644
--- a/arch/arm/mach-tegra/tegra20/clock.c
+++ b/arch/arm/mach-tegra/tegra20/clock.c
@@ -20,6 +20,8 @@
#include <fdtdec.h>
#include <linux/delay.h>
+#include <dt-bindings/clock/tegra20-car.h>
+
/*
* Clock types that we can use as a source. The Tegra20 has muxes for the
* peripheral clocks, and in most cases there are four options for the clock
@@ -576,6 +578,41 @@ enum periph_id clk_id_to_periph_id(int clk_id)
return clk_id;
}
}
+
+/*
+ * Convert a device tree clock ID to our PLL ID.
+ *
+ * @param clk_id Clock ID according to tegra20 device tree binding
+ * Return: clock ID, or CLOCK_ID_NONE if the clock ID is invalid
+ */
+enum clock_id clk_id_to_pll_id(int clk_id)
+{
+ switch (clk_id) {
+ case TEGRA20_CLK_PLL_C:
+ return CLOCK_ID_CGENERAL;
+ case TEGRA20_CLK_PLL_M:
+ return CLOCK_ID_MEMORY;
+ case TEGRA20_CLK_PLL_P:
+ return CLOCK_ID_PERIPH;
+ case TEGRA20_CLK_PLL_A:
+ return CLOCK_ID_AUDIO;
+ case TEGRA20_CLK_PLL_U:
+ return CLOCK_ID_USB;
+ case TEGRA20_CLK_PLL_D:
+ case TEGRA20_CLK_PLL_D_OUT0:
+ return CLOCK_ID_DISPLAY;
+ case TEGRA20_CLK_PLL_X:
+ return CLOCK_ID_XCPU;
+ case TEGRA20_CLK_PLL_E:
+ return CLOCK_ID_EPCI;
+ case TEGRA20_CLK_CLK_32K:
+ return CLOCK_ID_32KHZ;
+ case TEGRA20_CLK_CLK_M:
+ return CLOCK_ID_CLK_M;
+ default:
+ return CLOCK_ID_NONE;
+ }
+}
#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
void clock_early_init(void)
diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c
index 10c2478df7..1c991bbeab 100644
--- a/arch/arm/mach-tegra/tegra210/clock.c
+++ b/arch/arm/mach-tegra/tegra210/clock.c
@@ -22,6 +22,8 @@
#include <linux/bitops.h>
#include <linux/delay.h>
+#include <dt-bindings/clock/tegra210-car.h>
+
/*
* Clock types that we can use as a source. The Tegra210 has muxes for the
* peripheral clocks, and in most cases there are four options for the clock
@@ -930,6 +932,41 @@ enum periph_id clk_id_to_periph_id(int clk_id)
return clk_id;
}
}
+
+/*
+ * Convert a device tree clock ID to our PLL ID.
+ *
+ * @param clk_id Clock ID according to tegra210 device tree binding
+ * Return: clock ID, or CLOCK_ID_NONE if the clock ID is invalid
+ */
+enum clock_id clk_id_to_pll_id(int clk_id)
+{
+ switch (clk_id) {
+ case TEGRA210_CLK_PLL_C:
+ return CLOCK_ID_CGENERAL;
+ case TEGRA210_CLK_PLL_M:
+ return CLOCK_ID_MEMORY;
+ case TEGRA210_CLK_PLL_P:
+ return CLOCK_ID_PERIPH;
+ case TEGRA210_CLK_PLL_A:
+ return CLOCK_ID_AUDIO;
+ case TEGRA210_CLK_PLL_U:
+ return CLOCK_ID_USB;
+ case TEGRA210_CLK_PLL_D:
+ case TEGRA210_CLK_PLL_D_OUT0:
+ return CLOCK_ID_DISPLAY;
+ case TEGRA210_CLK_PLL_X:
+ return CLOCK_ID_XCPU;
+ case TEGRA210_CLK_PLL_E:
+ return CLOCK_ID_EPCI;
+ case TEGRA210_CLK_CLK_32K:
+ return CLOCK_ID_32KHZ;
+ case TEGRA210_CLK_CLK_M:
+ return CLOCK_ID_CLK_M;
+ default:
+ return CLOCK_ID_NONE;
+ }
+}
#endif /* CONFIG_OF_CONTROL */
/*
diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c
index cb16ef7cf3..3b0b84f8fd 100644
--- a/arch/arm/mach-tegra/tegra30/clock.c
+++ b/arch/arm/mach-tegra/tegra30/clock.c
@@ -19,6 +19,8 @@
#include <fdtdec.h>
#include <linux/delay.h>
+#include <dt-bindings/clock/tegra30-car.h>
+
/*
* Clock types that we can use as a source. The Tegra30 has muxes for the
* peripheral clocks, and in most cases there are four options for the clock
@@ -634,6 +636,41 @@ enum periph_id clk_id_to_periph_id(int clk_id)
return clk_id;
}
}
+
+/*
+ * Convert a device tree clock ID to our PLL ID.
+ *
+ * @param clk_id Clock ID according to tegra30 device tree binding
+ * Return: clock ID, or CLOCK_ID_NONE if the clock ID is invalid
+ */
+enum clock_id clk_id_to_pll_id(int clk_id)
+{
+ switch (clk_id) {
+ case TEGRA30_CLK_PLL_C:
+ return CLOCK_ID_CGENERAL;
+ case TEGRA30_CLK_PLL_M:
+ return CLOCK_ID_MEMORY;
+ case TEGRA30_CLK_PLL_P:
+ return CLOCK_ID_PERIPH;
+ case TEGRA30_CLK_PLL_A:
+ return CLOCK_ID_AUDIO;
+ case TEGRA30_CLK_PLL_U:
+ return CLOCK_ID_USB;
+ case TEGRA30_CLK_PLL_D:
+ case TEGRA30_CLK_PLL_D_OUT0:
+ return CLOCK_ID_DISPLAY;
+ case TEGRA30_CLK_PLL_X:
+ return CLOCK_ID_XCPU;
+ case TEGRA30_CLK_PLL_E:
+ return CLOCK_ID_EPCI;
+ case TEGRA30_CLK_CLK_32K:
+ return CLOCK_ID_32KHZ;
+ case TEGRA30_CLK_CLK_M:
+ return CLOCK_ID_CLK_M;
+ default:
+ return CLOCK_ID_NONE;
+ }
+}
#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
void clock_early_init(void)
--
2.37.2
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