[PATCH v1 02/16] ARM: t20/t30: swap host1x and disp1 clock parents

[Svyatoslav Ryhel]

According to mainline clock tables and TRM HOST1X
parent is PLLC, while DISP1 usually uses PLLP as
parent clock.

Tested-by: Andreas Westman Dorcsak <hedmoo at yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob at gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95 at gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95 at gmail.com>
---
 arch/arm/mach-tegra/tegra20/clock.c | 4 ++--
 arch/arm/mach-tegra/tegra30/clock.c | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c
index 3b50a81194..755167e068 100644
--- a/arch/arm/mach-tegra/tegra20/clock.c
+++ b/arch/arm/mach-tegra/tegra20/clock.c
@@ -758,8 +758,8 @@ struct periph_clk_init periph_clk_init_table[] = {
 	{ PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
-	{ PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
-	{ PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
+	{ PERIPH_ID_HOST1X, CLOCK_ID_CGENERAL },
+	{ PERIPH_ID_DISP1, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c
index 54855d6be7..cb16ef7cf3 100644
--- a/arch/arm/mach-tegra/tegra30/clock.c
+++ b/arch/arm/mach-tegra/tegra30/clock.c
@@ -805,8 +805,8 @@ struct periph_clk_init periph_clk_init_table[] = {
 	{ PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
-	{ PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
-	{ PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
+	{ PERIPH_ID_HOST1X, CLOCK_ID_CGENERAL },
+	{ PERIPH_ID_DISP1, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
 	{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
-- 
2.37.2