[PATCH v1 4/5] dt-bindings: clock: jh7110: Modify clock id to be same with Linux
Hal Feng
hal.feng at starfivetech.com
Fri Jul 7 12:50:10 CEST 2023
From: Xingyu Wu <xingyu.wu at starfivetech.com>
The clock id needs to be changed to be consistent with Linux.
Signed-off-by: Xingyu Wu <xingyu.wu at starfivetech.com>
Signed-off-by: Hal Feng <hal.feng at starfivetech.com>
---
.../dt-bindings/clock/starfive,jh7110-crg.h | 101 +++++++++---------
1 file changed, 51 insertions(+), 50 deletions(-)
diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
index 77b70e7a83..b51e3829ff 100644
--- a/include/dt-bindings/clock/starfive,jh7110-crg.h
+++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
@@ -8,6 +8,11 @@
#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__
#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__
+#define JH7110_SYSCLK_PLL0_OUT 0
+#define JH7110_SYSCLK_PLL1_OUT 1
+#define JH7110_SYSCLK_PLL2_OUT 2
+#define JH7110_PLLCLK_END 3
+
#define JH7110_SYSCLK_CPU_ROOT 0
#define JH7110_SYSCLK_CPU_CORE 1
#define JH7110_SYSCLK_CPU_BUS 2
@@ -199,59 +204,55 @@
#define JH7110_SYSCLK_TDM_CLK_TDM_N 188
#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189
-#define JH7110_SYSCLK_PLL0_OUT 190
-#define JH7110_SYSCLK_PLL1_OUT 191
-#define JH7110_SYSCLK_PLL2_OUT 192
-
-#define JH7110_SYSCLK_END 193
+#define JH7110_SYSCLK_END 190
-#define JH7110_AONCLK_OSC_DIV4 (JH7110_SYSCLK_END + 0)
-#define JH7110_AONCLK_APB_FUNC (JH7110_SYSCLK_END + 1)
-#define JH7110_AONCLK_GMAC0_AHB (JH7110_SYSCLK_END + 2)
-#define JH7110_AONCLK_GMAC0_AXI (JH7110_SYSCLK_END + 3)
-#define JH7110_AONCLK_GMAC0_RMII_RTX (JH7110_SYSCLK_END + 4)
-#define JH7110_AONCLK_GMAC0_TX (JH7110_SYSCLK_END + 5)
-#define JH7110_AONCLK_GMAC0_TX_INV (JH7110_SYSCLK_END + 6)
-#define JH7110_AONCLK_GMAC0_RX (JH7110_SYSCLK_END + 7)
-#define JH7110_AONCLK_GMAC0_RX_INV (JH7110_SYSCLK_END + 8)
-#define JH7110_AONCLK_OTPC_APB (JH7110_SYSCLK_END + 9)
-#define JH7110_AONCLK_RTC_APB (JH7110_SYSCLK_END + 10)
-#define JH7110_AONCLK_RTC_INTERNAL (JH7110_SYSCLK_END + 11)
-#define JH7110_AONCLK_RTC_32K (JH7110_SYSCLK_END + 12)
-#define JH7110_AONCLK_RTC_CAL (JH7110_SYSCLK_END + 13)
+#define JH7110_AONCLK_OSC_DIV4 0
+#define JH7110_AONCLK_APB_FUNC 1
+#define JH7110_AONCLK_GMAC0_AHB 2
+#define JH7110_AONCLK_GMAC0_AXI 3
+#define JH7110_AONCLK_GMAC0_RMII_RTX 4
+#define JH7110_AONCLK_GMAC0_TX 5
+#define JH7110_AONCLK_GMAC0_TX_INV 6
+#define JH7110_AONCLK_GMAC0_RX 7
+#define JH7110_AONCLK_GMAC0_RX_INV 8
+#define JH7110_AONCLK_OTPC_APB 9
+#define JH7110_AONCLK_RTC_APB 10
+#define JH7110_AONCLK_RTC_INTERNAL 11
+#define JH7110_AONCLK_RTC_32K 12
+#define JH7110_AONCLK_RTC_CAL 13
-#define JH7110_AONCLK_END (JH7110_SYSCLK_END + 14)
+#define JH7110_AONCLK_END 14
-#define JH7110_STGCLK_HIFI4_CORE (JH7110_AONCLK_END + 0)
-#define JH7110_STGCLK_USB_APB (JH7110_AONCLK_END + 1)
-#define JH7110_STGCLK_USB_UTMI_APB (JH7110_AONCLK_END + 2)
-#define JH7110_STGCLK_USB_AXI (JH7110_AONCLK_END + 3)
-#define JH7110_STGCLK_USB_LPM (JH7110_AONCLK_END + 4)
-#define JH7110_STGCLK_USB_STB (JH7110_AONCLK_END + 5)
-#define JH7110_STGCLK_USB_APP_125 (JH7110_AONCLK_END + 6)
-#define JH7110_STGCLK_USB_REFCLK (JH7110_AONCLK_END + 7)
-#define JH7110_STGCLK_PCIE0_AXI (JH7110_AONCLK_END + 8)
-#define JH7110_STGCLK_PCIE0_APB (JH7110_AONCLK_END + 9)
-#define JH7110_STGCLK_PCIE0_TL (JH7110_AONCLK_END + 10)
-#define JH7110_STGCLK_PCIE1_AXI (JH7110_AONCLK_END + 11)
-#define JH7110_STGCLK_PCIE1_APB (JH7110_AONCLK_END + 12)
-#define JH7110_STGCLK_PCIE1_TL (JH7110_AONCLK_END + 13)
-#define JH7110_STGCLK_PCIE01_MAIN (JH7110_AONCLK_END + 14)
-#define JH7110_STGCLK_SEC_HCLK (JH7110_AONCLK_END + 15)
-#define JH7110_STGCLK_SEC_MISCAHB (JH7110_AONCLK_END + 16)
-#define JH7110_STGCLK_MTRX_GRP0_MAIN (JH7110_AONCLK_END + 17)
-#define JH7110_STGCLK_MTRX_GRP0_BUS (JH7110_AONCLK_END + 18)
-#define JH7110_STGCLK_MTRX_GRP0_STG (JH7110_AONCLK_END + 19)
-#define JH7110_STGCLK_MTRX_GRP1_MAIN (JH7110_AONCLK_END + 20)
-#define JH7110_STGCLK_MTRX_GRP1_BUS (JH7110_AONCLK_END + 21)
-#define JH7110_STGCLK_MTRX_GRP1_STG (JH7110_AONCLK_END + 22)
-#define JH7110_STGCLK_MTRX_GRP1_HIFI (JH7110_AONCLK_END + 23)
-#define JH7110_STGCLK_E2_RTC (JH7110_AONCLK_END + 24)
-#define JH7110_STGCLK_E2_CORE (JH7110_AONCLK_END + 25)
-#define JH7110_STGCLK_E2_DBG (JH7110_AONCLK_END + 26)
-#define JH7110_STGCLK_DMA1P_AXI (JH7110_AONCLK_END + 27)
-#define JH7110_STGCLK_DMA1P_AHB (JH7110_AONCLK_END + 28)
+#define JH7110_STGCLK_HIFI4_CORE 0
+#define JH7110_STGCLK_USB_APB 1
+#define JH7110_STGCLK_USB_UTMI_APB 2
+#define JH7110_STGCLK_USB_AXI 3
+#define JH7110_STGCLK_USB_LPM 4
+#define JH7110_STGCLK_USB_STB 5
+#define JH7110_STGCLK_USB_APP_125 6
+#define JH7110_STGCLK_USB_REFCLK 7
+#define JH7110_STGCLK_PCIE0_AXI 8
+#define JH7110_STGCLK_PCIE0_APB 9
+#define JH7110_STGCLK_PCIE0_TL 10
+#define JH7110_STGCLK_PCIE1_AXI 11
+#define JH7110_STGCLK_PCIE1_APB 12
+#define JH7110_STGCLK_PCIE1_TL 13
+#define JH7110_STGCLK_PCIE01_MAIN 14
+#define JH7110_STGCLK_SEC_HCLK 15
+#define JH7110_STGCLK_SEC_MISCAHB 16
+#define JH7110_STGCLK_MTRX_GRP0_MAIN 17
+#define JH7110_STGCLK_MTRX_GRP0_BUS 18
+#define JH7110_STGCLK_MTRX_GRP0_STG 19
+#define JH7110_STGCLK_MTRX_GRP1_MAIN 20
+#define JH7110_STGCLK_MTRX_GRP1_BUS 21
+#define JH7110_STGCLK_MTRX_GRP1_STG 22
+#define JH7110_STGCLK_MTRX_GRP1_HIFI 23
+#define JH7110_STGCLK_E2_RTC 24
+#define JH7110_STGCLK_E2_CORE 25
+#define JH7110_STGCLK_E2_DBG 26
+#define JH7110_STGCLK_DMA1P_AXI 27
+#define JH7110_STGCLK_DMA1P_AHB 28
-#define JH7110_STGCLK_END (JH7110_AONCLK_END + 29)
+#define JH7110_STGCLK_END 29
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */
--
2.38.1
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