[PATCH v1 1/5] clk: starfive: jh7110: Separate the PLL driver
Hal Feng
hal.feng at starfivetech.com
Fri Jul 7 12:50:07 CEST 2023
From: Xingyu Wu <xingyu.wu at starfivetech.com>
Drop the PLL part in SYSCRG driver and separate to be a single
PLL driver of which the compatible is "starfive,jh7110-pll".
Signed-off-by: Xingyu Wu <xingyu.wu at starfivetech.com>
Signed-off-by: Hal Feng <hal.feng at starfivetech.com>
---
drivers/clk/starfive/clk-jh7110-pll.c | 86 +++++++++++++++++++++++++--
drivers/clk/starfive/clk-jh7110.c | 25 +-------
drivers/clk/starfive/clk.h | 57 ------------------
3 files changed, 84 insertions(+), 84 deletions(-)
delete mode 100644 drivers/clk/starfive/clk.h
diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c
index 02e6d9000e..48c08bbe95 100644
--- a/drivers/clk/starfive/clk-jh7110-pll.c
+++ b/drivers/clk/starfive/clk-jh7110-pll.c
@@ -3,6 +3,7 @@
* Copyright (C) 2022-23 StarFive Technology Co., Ltd.
*
* Author: Yanhong Wang <yanhong.wang at starfivetech.com>
+ * Xingyu Wu <xingyu.wu at starfivetech.com>
*/
#include <common.h>
@@ -11,13 +12,13 @@
#include <clk-uclass.h>
#include <div64.h>
#include <dm/device.h>
+#include <dm/read.h>
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
#include <linux/bitops.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/err.h>
-#include "clk.h"
-
#define UBOOT_DM_CLK_JH7110_PLLX "jh7110_clk_pllx"
#define PLL_PD_OFF 1
@@ -30,6 +31,45 @@
#define CLK_DDR_BUS_PLL1_DIV4 2
#define CLK_DDR_BUS_PLL1_DIV8 3
+enum starfive_pll_type {
+ PLL0 = 0,
+ PLL1,
+ PLL2,
+ PLL_MAX = PLL2
+};
+
+struct starfive_pllx_rate {
+ u64 rate;
+ u32 prediv;
+ u32 fbdiv;
+ u32 frac;
+};
+
+struct starfive_pllx_offset {
+ u32 pd;
+ u32 prediv;
+ u32 fbdiv;
+ u32 frac;
+ u32 postdiv1;
+ u32 dacpd;
+ u32 dsmpd;
+ u32 pd_mask;
+ u32 prediv_mask;
+ u32 fbdiv_mask;
+ u32 frac_mask;
+ u32 postdiv1_mask;
+ u32 dacpd_mask;
+ u32 dsmpd_mask;
+};
+
+struct starfive_pllx_clk {
+ enum starfive_pll_type type;
+ const struct starfive_pllx_offset *offset;
+ const struct starfive_pllx_rate *rate_table;
+ int rate_count;
+ int flags;
+};
+
struct clk_jh7110_pllx {
struct clk clk;
void __iomem *base;
@@ -271,7 +311,7 @@ static ulong jh7110_pllx_set_rate(struct clk *clk, ulong drate)
return jh7110_pllx_recalc_rate(clk);
}
-static const struct clk_ops clk_jh7110_ops = {
+static const struct clk_ops jh7110_clk_pllx_ops = {
.set_rate = jh7110_pllx_set_rate,
.get_rate = jh7110_pllx_recalc_rate,
};
@@ -314,8 +354,46 @@ struct clk *starfive_jh7110_pll(const char *name, const char *parent_name,
return clk;
}
+/* PLLx clock implementation */
U_BOOT_DRIVER(jh7110_clk_pllx) = {
.name = UBOOT_DM_CLK_JH7110_PLLX,
.id = UCLASS_CLK,
- .ops = &clk_jh7110_ops,
+ .ops = &jh7110_clk_pllx_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+static int jh7110_pll_clk_probe(struct udevice *dev)
+{
+ void __iomem *reg = (void __iomem *)dev_read_addr_ptr(dev->parent);
+ fdt_addr_t sysreg = ofnode_get_addr(ofnode_by_compatible(ofnode_null(),
+ "starfive,jh7110-syscrg"));
+
+ if (sysreg == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ clk_dm(JH7110_SYSCLK_PLL0_OUT,
+ starfive_jh7110_pll("pll0_out", "oscillator", reg,
+ (void __iomem *)sysreg, &starfive_jh7110_pll0));
+ clk_dm(JH7110_SYSCLK_PLL1_OUT,
+ starfive_jh7110_pll("pll1_out", "oscillator", reg,
+ (void __iomem *)sysreg, &starfive_jh7110_pll1));
+ clk_dm(JH7110_SYSCLK_PLL2_OUT,
+ starfive_jh7110_pll("pll2_out", "oscillator", reg,
+ (void __iomem *)sysreg, &starfive_jh7110_pll2));
+
+ return 0;
+}
+
+static const struct udevice_id jh7110_pll_clk_of_match[] = {
+ { .compatible = "starfive,jh7110-pll", },
+ { }
+};
+
+/* PLL clk device */
+U_BOOT_DRIVER(jh7110_pll_clk) = {
+ .name = "jh7110_pll_clk",
+ .id = UCLASS_CLK,
+ .of_match = jh7110_pll_clk_of_match,
+ .probe = jh7110_pll_clk_probe,
+ .ops = &ccf_clk_ops,
};
diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c
index a74b70906a..d2aea8d7d1 100644
--- a/drivers/clk/starfive/clk-jh7110.c
+++ b/drivers/clk/starfive/clk-jh7110.c
@@ -3,6 +3,7 @@
* Copyright (C) 2022-23 StarFive Technology Co., Ltd.
*
* Author: Yanhong Wang <yanhong.wang at starfivetech.com>
+ * Xingyu Wu <xingyu.wu at starfivetech.com>
*/
#include <common.h>
@@ -16,8 +17,6 @@
#include <log.h>
#include <linux/clk-provider.h>
-#include "clk.h"
-
#define STARFIVE_CLK_ENABLE_SHIFT 31 /* [31] */
#define STARFIVE_CLK_INVERT_SHIFT 30 /* [30] */
#define STARFIVE_CLK_MUX_SHIFT 24 /* [29:24] */
@@ -230,28 +229,8 @@ static struct clk *starfive_clk_gate_divider(void __iomem *reg,
static int jh7110_syscrg_init(struct udevice *dev)
{
struct jh7110_clk_priv *priv = dev_get_priv(dev);
- struct ofnode_phandle_args args;
- fdt_addr_t addr;
struct clk *pclk;
- int ret;
-
- ret = ofnode_parse_phandle_with_args(dev->node_, "starfive,sys-syscon", NULL, 0, 0, &args);
- if (ret)
- return ret;
-
- addr = ofnode_get_addr(args.node);
- if (addr == FDT_ADDR_T_NONE)
- return -EINVAL;
-
- clk_dm(JH7110_SYSCLK_PLL0_OUT,
- starfive_jh7110_pll("pll0_out", "oscillator", (void __iomem *)addr,
- priv->reg, &starfive_jh7110_pll0));
- clk_dm(JH7110_SYSCLK_PLL1_OUT,
- starfive_jh7110_pll("pll1_out", "oscillator", (void __iomem *)addr,
- priv->reg, &starfive_jh7110_pll1));
- clk_dm(JH7110_SYSCLK_PLL2_OUT,
- starfive_jh7110_pll("pll2_out", "oscillator", (void __iomem *)addr,
- priv->reg, &starfive_jh7110_pll2));
+
clk_dm(JH7110_SYSCLK_CPU_ROOT,
starfive_clk_mux(priv->reg, "cpu_root",
OFFSET(JH7110_SYSCLK_CPU_ROOT), 1,
diff --git a/drivers/clk/starfive/clk.h b/drivers/clk/starfive/clk.h
deleted file mode 100644
index 4dee12fe89..0000000000
--- a/drivers/clk/starfive/clk.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2022 Starfive, Inc.
- * Author: Yanhong Wang <yanhong.wang at starfivetech.com>
- *
- */
-
-#ifndef __CLK_STARFIVE_H
-#define __CLK_STARFIVE_H
-
-enum starfive_pll_type {
- PLL0 = 0,
- PLL1,
- PLL2,
- PLL_MAX = PLL2
-};
-
-struct starfive_pllx_rate {
- u64 rate;
- u32 prediv;
- u32 fbdiv;
- u32 frac;
-};
-
-struct starfive_pllx_offset {
- u32 pd;
- u32 prediv;
- u32 fbdiv;
- u32 frac;
- u32 postdiv1;
- u32 dacpd;
- u32 dsmpd;
- u32 pd_mask;
- u32 prediv_mask;
- u32 fbdiv_mask;
- u32 frac_mask;
- u32 postdiv1_mask;
- u32 dacpd_mask;
- u32 dsmpd_mask;
-};
-
-struct starfive_pllx_clk {
- enum starfive_pll_type type;
- const struct starfive_pllx_offset *offset;
- const struct starfive_pllx_rate *rate_table;
- int rate_count;
- int flags;
-};
-
-extern struct starfive_pllx_clk starfive_jh7110_pll0;
-extern struct starfive_pllx_clk starfive_jh7110_pll1;
-extern struct starfive_pllx_clk starfive_jh7110_pll2;
-
-struct clk *starfive_jh7110_pll(const char *name, const char *parent_name,
- void __iomem *base, void __iomem *sysreg,
- const struct starfive_pllx_clk *pll_clk);
-#endif
--
2.38.1
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