[PATCH] ARM: stm32: Power cycle Buck3 in reset on DHSOM

[Marek Vasut]

On 7/4/23 23:55, Marek Vasut wrote:
> On 5/18/23 00:02, Marek Vasut wrote:
>> In case the DHSOM is in suspend state and either reset button is pushed
>> or IWDG2 triggers a watchdog reset, then DRAM initialization could fail
>> as follows:
>>
>>    "
>>    RAM: DDR3L 32bits 2x4Gb 533MHz
>>    DDR invalid size : 0x4, expected 0x40000000
>>    DRAM init failed: -22
>>    ### ERROR ### Please RESET the board ###
>>    "
>>
>> Avoid this failure by not keeping any Buck regulators enabled during 
>> reset,
>> let the SoC and DRAMs power cycle fully. Since the change which keeps 
>> Buck3
>> VDD enabled during reset is ST specific, move this addition to ST 
>> specific
>> SPL board initialization so that it wouldn't affect the DHSOM .
>>
>> Signed-off-by: Marek Vasut <marex at denx.de>
>> ---
>> NOTE: This is 2023.07 material
> 
> I don't see this one in 2023.07 yet, can you please pick it and send PR?

Sadly, this bugfix has not made it into 2023.07, even though the fix was 
posted a month and half before the actual release.