[PATCH v1 11/16] serial: pl01x: Modify pending callback to test if transmit FIFO is empty

[sbabic at denx.de]

> Before this change the FR_TXFF (Transmit FIFO full) bit (5 in
> HW_UARTDBG_FR) has been used to assess if there is still data pending
> to be sent via UART.
> This approach is problematic, as it may happen that serial is in the
> middle of transmission (so the TX FIFO is NOT full anymore) and this
> test returns true infinitely. As a result, for example in _serial_flush()
> DM serial function we are locked in endless while().
> The fix here is to test explicitly if the TX FIFO is empty.
> Signed-off-by: Lukasz Majewski <lukma at denx.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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