[RFC PATCH] riscv: sifive: fu70: downclock CPU clock for stability

[Icenowy Zheng]

在 2023-07-12星期三的 14:13 +0100，Maciej W. Rozycki写道：
> On Wed, 28 Jun 2023, Icenowy Zheng wrote:
> 
> > When building the package `rustc` for AOSC OS on HiFive Unmatched,
> > random SIGSEGV prevents the package from getting correctly built.
> > Downclocking the CPU PLL clock seems to allow rustc to be built,
> > although taking much more time.
> > 
> > Downclock the CPU PLL frequency for stability.
> 
>  FYI, I've been observing occasional (less than 1 bit per 10GiB of
> data 
> moved) single-bit data corruption on DRAM writes with my HiFive
> Unmatched, 
> but your change does not appear to make any difference with my
> system.
> 
>  FWIW, given the price and amount of DRAM used I think it makes no
> sense 
> to build computers equipped with a DRAM subsystem without ECC
> nowadays.

Well the HiFive Unmatched board looks like it has a DRAM chip for ECC,
but whether this is activated is not known...

> 
>   Maciej