[PATCH v2 4/6] mtd: nand: pxa3xx: Enable devbus/nand arbiter on Armada 8K

[Stefan Roese]

On 7/10/23 00:47, Chris Packham wrote:
> The CN9130 SoC (an ARMADA 8K type) has both a NAND Flash Controller and
> a generic local bus controller (Device Bus Controller) that share common
> pins.
> 
> With a board design that incorporates both a NAND flash and uses
> the Device Bus (in our case for an SRAM) accessing the Device Bus device
> fails unless the NfArbiterEn bit is set. Setting the bit enables
> arbitration between the Device Bus and the NAND flash.
> 
> Since there is no obvious downside in enabling this for designs that
> don't require arbitration, we always enable it.
> 
> Signed-off-by: Chris Packham <judge.packham at gmail.com>

Reviewed-by: Stefan Roese <sr at denx.de>

Thanks,
Stefan

> ---
>   drivers/mtd/nand/raw/pxa3xx_nand.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c b/drivers/mtd/nand/raw/pxa3xx_nand.c
> index 9dee580ab9c2..d502e967f92c 100644
> --- a/drivers/mtd/nand/raw/pxa3xx_nand.c
> +++ b/drivers/mtd/nand/raw/pxa3xx_nand.c
> @@ -125,6 +125,7 @@ DECLARE_GLOBAL_DATA_PTR;
>   /* System control register and bit to enable NAND on some SoCs */
>   #define GENCONF_SOC_DEVICE_MUX	0x208
>   #define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0)
> +#define GENCONF_SOC_DEVICE_MUX_NFC_DEVBUS_ARB_EN BIT(27)
>   
>   /*
>    * This should be large enough to read 'ONFI' and 'JEDEC'.
> @@ -1739,7 +1740,7 @@ static int alloc_nand_resource(struct udevice *dev, struct pxa3xx_nand_info *inf
>   			return PTR_ERR(sysctrl_base);
>   
>   		regmap_read(sysctrl_base, GENCONF_SOC_DEVICE_MUX, &reg);
> -		reg |= GENCONF_SOC_DEVICE_MUX_NFC_EN;
> +		reg |= GENCONF_SOC_DEVICE_MUX_NFC_EN | GENCONF_SOC_DEVICE_MUX_NFC_DEVBUS_ARB_EN;
>   		regmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX, reg);
>   	}
>   

Viele Grüße,
Stefan Roese

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