[PATCH 16/18] riscv: define a cache line size for the generic CPU

[Bin Meng]

From: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>

The USB 3.0 driver xhci-mem.c requires CONFIG_SYS_CACHELINE_SIZE to be set.

Define the cache line size for QEMU on RISC-V to be 64 bytes.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
Reviewed-by: Bin Meng <bmeng at tinylab.org>
Signed-off-by: Bin Meng <bmeng at tinylab.org>
---

 arch/riscv/cpu/generic/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig
index 897765c3c6..2baba22992 100644
--- a/arch/riscv/cpu/generic/Kconfig
+++ b/arch/riscv/cpu/generic/Kconfig
@@ -6,6 +6,7 @@ config GENERIC_RISCV
 	bool
 	select BINMAN if SPL
 	select ARCH_EARLY_INIT_R
+	select SYS_CACHE_SHIFT_6
 	imply CPU
 	imply CPU_RISCV
 	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
-- 
2.34.1