[PATCH 3/5] board: rockchip: Add Pine64 SOQuartz on Model A

Sun Jul 23 17:08:27 CEST 2023

On 2023-07-23 16:55, Jonas Karlman wrote:
> The Pine64 SOQuartz Model A board is a carrier board for the SOQuartz
> CM4-compatible compute module. It exposes PCIe, ethernet, USB, HDMI,
> CSI, DSI, eDP and a 40 pin GPIO header, and is powered by 12V DC.
> 
> Features tested with a SOQuartz 4GB v1.1 2022-07-11:
> - SD-card boot
> - eMMC boot
> - PCIe/NVMe/AHCI
> - USB host
> 
> Device tree is imported from linux v6.4.
> 
> Co-developed-by: Nicolas Frattaroli <frattaroli.nicolas at gmail.com>
> Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas at gmail.com>
> Signed-off-by: Jonas Karlman <jonas at kwiboo.se>
> ---

[...]

Boot log with ROCKCHIP_TPL=rk3566_ddr_1056MHz_v1.17.bin and
BL31=rk3568_bl31_v1.43.elf:
DDR V1.17 992b933606 typ 23/04/25-10:10:19
ln
LP4/4x derate en, other dram:1x trefi
ddrconfig:0
LPDDR4X, 324MHz
BW=32 Col=10 Bk=8 CS0 Row=17 CS=1 Die BW=16 Size=4096MB
tdqss: cs0 dqs0: 24ps, dqs1: -48ps, dqs2: -24ps, dqs3: -48ps,

change to: 324MHz
clk skew:0x60

change to: 528MHz
clk skew:0x58

change to: 780MHz
clk skew:0x58

change to: 1056MHz(final freq)
PHY drv:clk:36,ca:36,DQ:29,odt:60
vrefinner:16%, vrefout:22%
dram drv:40,odt:80
vref_ca:00000071
clk skew:0x29
cs 0:
the read training result:
DQS0:0x3a, DQS1:0x3f, DQS2:0x3c, DQS3:0x39,
min  : 0x9  0x8  0x3  0x1  0x2  0x3  0x7  0x6 , 0x7  0x1  0x2  0x2  0x7  0xf 0x10  0xc ,
       0x7  0x6  0x6  0x6  0x5  0x1  0x5  0x4 , 0x1  0x2  0x7  0x2  0x7  0x6  0x6  0x4 ,
mid  :0x27 0x27 0x22 0x1e 0x20 0x21 0x25 0x25 ,0x25 0x22 0x22 0x22 0x26 0x2e 0x2f 0x2b ,
      0x27 0x26 0x25 0x24 0x23 0x20 0x24 0x23 ,0x20 0x21 0x25 0x21 0x26 0x24 0x24 0x22 ,
max  :0x46 0x47 0x41 0x3b 0x3f 0x40 0x44 0x45 ,0x44 0x43 0x42 0x43 0x46 0x4e 0x4e 0x4b ,
      0x47 0x46 0x45 0x43 0x42 0x40 0x44 0x43 ,0x40 0x40 0x44 0x40 0x45 0x42 0x42 0x40 ,
range:0x3d 0x3f 0x3e 0x3a 0x3d 0x3d 0x3d 0x3f ,0x3d 0x42 0x40 0x41 0x3f 0x3f 0x3e 0x3f ,
      0x40 0x40 0x3f 0x3d 0x3d 0x3f 0x3f 0x3f ,0x3f 0x3e 0x3d 0x3e 0x3e 0x3c 0x3c 0x3c ,
the write training result:
DQS0:0x2c, DQS1:0x23, DQS2:0x26, DQS3:0x23,
min  :0x52 0x55 0x50 0x4d 0x4d 0x4e 0x53 0x54 0x54 ,0x43 0x3f 0x3f 0x41 0x46 0x4c 0x4c 0x4a 0x45 ,
      0x4a 0x4a 0x49 0x49 0x48 0x45 0x48 0x49 0x49 ,0x42 0x43 0x48 0x45 0x48 0x47 0x45 0x46 0x47 ,
mid  :0x6f 0x72 0x6c 0x69 0x69 0x6a 0x6f 0x6f 0x70 ,0x5f 0x5c 0x5b 0x5d 0x62 0x69 0x68 0x66 0x61 ,
      0x67 0x67 0x66 0x66 0x64 0x61 0x63 0x65 0x66 ,0x5f 0x5f 0x65 0x61 0x65 0x64 0x61 0x63 0x64 ,
max  :0x8c 0x8f 0x89 0x85 0x86 0x87 0x8c 0x8b 0x8d ,0x7c 0x7a 0x77 0x79 0x7e 0x86 0x84 0x83 0x7d ,
      0x85 0x84 0x83 0x83 0x80 0x7d 0x7f 0x82 0x83 ,0x7c 0x7c 0x83 0x7d 0x83 0x81 0x7e 0x80 0x81 ,
range:0x3a 0x3a 0x39 0x38 0x39 0x39 0x39 0x37 0x39 ,0x39 0x3b 0x38 0x38 0x38 0x3a 0x38 0x39 0x38 ,
      0x3b 0x3a 0x3a 0x3a 0x38 0x38 0x37 0x39 0x3a ,0x3a 0x39 0x3b 0x38 0x3b 0x3a 0x39 0x3a 0x3a ,
CA Training result:
cs:0 min  :0x3c 0x3a 0x36 0x37 0x38 0x30 0x38 ,0x3f 0x38 0x39 0x35 0x38 0x32 0x3a ,
cs:0 mid  :0x7a 0x7c 0x73 0x77 0x75 0x71 0x67 ,0x7b 0x78 0x77 0x76 0x77 0x73 0x69 ,
cs:0 max  :0xb8 0xbe 0xb1 0xb7 0xb3 0xb3 0x97 ,0xb7 0xb9 0xb5 0xb7 0xb6 0xb4 0x98 ,
cs:0 range:0x7c 0x84 0x7b 0x80 0x7b 0x83 0x5f ,0x78 0x81 0x7c 0x82 0x7e 0x82 0x5e ,
out

U-Boot SPL 2023.07 (Jul 23 2023 - 13:07:31 +0000)
rockchip_sdhci_probe clk set rate fail!
Trying to boot from MMC2
## Checking hash(es) for config config-1 ... OK
## Checking hash(es) for Image atf-1 ... sha256+ OK
## Checking hash(es) for Image u-boot ... sha256+ OK
## Checking hash(es) for Image fdt-1 ... sha256+ OK
## Checking hash(es) for Image atf-2 ... sha256+ OK
## Checking hash(es) for Image atf-3 ... sha256+ OK
## Checking hash(es) for Image atf-4 ... sha256+ OK
## Checking hash(es) for Image atf-5 ... sha256+ OK
## Checking hash(es) for Image atf-6 ... sha256+ OK
INFO:    Preloader serial: 2
NOTICE:  BL31: v2.3():v2.3-607-gbf602aff1:cl
NOTICE:  BL31: Built : 10:16:03, Jun  5 2023
INFO:    GICv3 without legacy support detected.
INFO:    ARM GICv3 driver initialized in EL3
INFO:    pmu v1 is valid 220114
INFO:    dfs DDR fsp_param[0].freq_mhz= 1056MHz
INFO:    dfs DDR fsp_param[1].freq_mhz= 324MHz
INFO:    dfs DDR fsp_param[2].freq_mhz= 528MHz
INFO:    dfs DDR fsp_param[3].freq_mhz= 780MHz
INFO:    Using opteed sec cpu_context!
INFO:    boot cpu mask: 0
INFO:    BL31: Initializing runtime services
WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
ERROR:   Error initializing runtime service opteed_fast
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0xa00000
INFO:    SPSR = 0x3c9

U-Boot 2023.07 (Jul 23 2023 - 13:07:31 +0000)

Model: PINE64 RK3566 SOQuartz on Model A carrier board
DRAM:  4 GiB (effective 3.7 GiB)
PMIC:  RK8090 (on=0x40, off=0x00)
Core:  315 devices, 27 uclasses, devicetree: separate
MMC:   rockchip_sdhci_probe clk set rate fail!
mmc at fe2b0000: 1, mmc at fe2c0000: 2, mmc at fe310000: 0
Loading Environment from nowhere... OK
In:    serial at fe660000
Out:   serial at fe660000
Err:   serial at fe660000
Model: PINE64 RK3566 SOQuartz on Model A carrier board
Net:   No ethernet found.

Hit any key to stop autoboot:  0
=>

Regards,
Jonas