[PATCH 5/5] board: rockchip: Add Pine64 SOQuartz on CM4-IO

Jonas Karlman jonas at kwiboo.se
Sun Jul 23 17:10:51 CEST 2023

On 2023-07-23 16:55, Jonas Karlman wrote:
> The Pine64 SOQuartz compute module is mostly pin-compatible with the RPi
> CM4 form factor. Therefore, it can slot into the official Raspberry Pi
> CM4 IO carrier board. Add this configuration to U-Boot.
> Features tested with a SOQuartz 4GB v1.1 2022-07-11:
> - SD-card boot
> - eMMC boot
> - USB host
> Device tree is imported from linux v6.4.
> Co-developed-by: Nicolas Frattaroli <frattaroli.nicolas at gmail.com>
> Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas at gmail.com>
> Signed-off-by: Jonas Karlman <jonas at kwiboo.se>
> ---


Boot log with ROCKCHIP_TPL=rk3566_ddr_1056MHz_v1.17.bin and

DDR V1.17 992b933606 typ 23/04/25-10:10:19
LP4/4x derate en, other dram:1x trefi
BW=32 Col=10 Bk=8 CS0 Row=17 CS=1 Die BW=16 Size=4096MB
tdqss: cs0 dqs0: -24ps, dqs1: -72ps, dqs2: -24ps, dqs3: -72ps,

change to: 324MHz
clk skew:0x61

change to: 528MHz
clk skew:0x58

change to: 780MHz
clk skew:0x58

change to: 1056MHz(final freq)
PHY drv:clk:36,ca:36,DQ:29,odt:60
vrefinner:16%, vrefout:22%
dram drv:40,odt:80
clk skew:0x2c
cs 0:
the read training result:
DQS0:0x3a, DQS1:0x3c, DQS2:0x3b, DQS3:0x37,
min  : 0xa  0x9  0x5  0x1  0x4  0x4  0x9  0x7 , 0x6  0x2  0x2  0x1  0x8  0xe  0xe  0xb ,
       0x8  0x6  0x8  0x6  0x5  0x2  0x5  0x6 , 0x1  0x1  0x6  0x1  0x6  0x3  0x3  0x2 ,
mid  :0x28 0x28 0x23 0x1f 0x22 0x22 0x27 0x25 ,0x24 0x20 0x21 0x21 0x25 0x2c 0x2d 0x29 ,
      0x27 0x25 0x25 0x24 0x23 0x20 0x23 0x24 ,0x20 0x1f 0x24 0x1f 0x24 0x22 0x21 0x20 ,
max  :0x46 0x47 0x41 0x3d 0x40 0x40 0x45 0x44 ,0x43 0x3f 0x40 0x41 0x43 0x4b 0x4c 0x48 ,
      0x46 0x45 0x43 0x43 0x41 0x3f 0x42 0x42 ,0x3f 0x3d 0x42 0x3d 0x42 0x41 0x40 0x3e ,
range:0x3c 0x3e 0x3c 0x3c 0x3c 0x3c 0x3c 0x3d ,0x3d 0x3d 0x3e 0x40 0x3b 0x3d 0x3e 0x3d ,
      0x3e 0x3f 0x3b 0x3d 0x3c 0x3d 0x3d 0x3c ,0x3e 0x3c 0x3c 0x3c 0x3c 0x3e 0x3d 0x3c ,
the write training result:
DQS0:0x29, DQS1:0x23, DQS2:0x29, DQS3:0x23,
min  :0x51 0x55 0x4e 0x4b 0x4d 0x4d 0x52 0x53 0x55 ,0x46 0x43 0x43 0x46 0x49 0x4e 0x4f 0x4e 0x49 ,
      0x4d 0x4d 0x4e 0x4d 0x4b 0x48 0x4c 0x4e 0x4d ,0x44 0x46 0x48 0x46 0x4a 0x47 0x46 0x47 0x49 ,
mid  :0x6e 0x71 0x6a 0x67 0x69 0x69 0x6e 0x6e 0x70 ,0x62 0x60 0x5f 0x62 0x65 0x6b 0x6b 0x6a 0x66 ,
      0x6a 0x6a 0x6a 0x69 0x67 0x65 0x68 0x69 0x69 ,0x60 0x61 0x65 0x62 0x66 0x64 0x62 0x63 0x65 ,
max  :0x8b 0x8d 0x86 0x83 0x85 0x85 0x8a 0x89 0x8b ,0x7f 0x7d 0x7b 0x7e 0x82 0x88 0x88 0x86 0x83 ,
      0x88 0x87 0x86 0x86 0x84 0x82 0x84 0x85 0x86 ,0x7c 0x7c 0x83 0x7e 0x83 0x81 0x7e 0x80 0x81 ,
range:0x3a 0x38 0x38 0x38 0x38 0x38 0x38 0x36 0x36 ,0x39 0x3a 0x38 0x38 0x39 0x3a 0x39 0x38 0x3a ,
      0x3b 0x3a 0x38 0x39 0x39 0x3a 0x38 0x37 0x39 ,0x38 0x36 0x3b 0x38 0x39 0x3a 0x38 0x39 0x38 ,
CA Training result:
cs:0 min  :0x3c 0x3c 0x35 0x36 0x37 0x30 0x39 ,0x3b 0x36 0x39 0x36 0x38 0x33 0x3b ,
cs:0 mid  :0x7a 0x7c 0x73 0x77 0x75 0x71 0x68 ,0x79 0x77 0x77 0x76 0x75 0x73 0x69 ,
cs:0 max  :0xb9 0xbd 0xb1 0xb8 0xb4 0xb3 0x97 ,0xb7 0xb8 0xb5 0xb7 0xb3 0xb4 0x98 ,
cs:0 range:0x7d 0x81 0x7c 0x82 0x7d 0x83 0x5e ,0x7c 0x82 0x7c 0x81 0x7b 0x81 0x5d ,

U-Boot SPL 2023.07 (Jul 23 2023 - 13:39:45 +0000)
rockchip_sdhci_probe clk set rate fail!
Trying to boot from MMC2
## Checking hash(es) for config config-1 ... OK
## Checking hash(es) for Image atf-1 ... sha256+ OK
## Checking hash(es) for Image u-boot ... sha256+ OK
## Checking hash(es) for Image fdt-1 ... sha256+ OK
## Checking hash(es) for Image atf-2 ... sha256+ OK
## Checking hash(es) for Image atf-3 ... sha256+ OK
## Checking hash(es) for Image atf-4 ... sha256+ OK
## Checking hash(es) for Image atf-5 ... sha256+ OK
## Checking hash(es) for Image atf-6 ... sha256+ OK
INFO:    Preloader serial: 2
NOTICE:  BL31: v2.3():v2.3-607-gbf602aff1:cl
NOTICE:  BL31: Built : 10:16:03, Jun  5 2023
INFO:    GICv3 without legacy support detected.
INFO:    ARM GICv3 driver initialized in EL3
INFO:    pmu v1 is valid 220114
INFO:    dfs DDR fsp_param[0].freq_mhz= 1056MHz
INFO:    dfs DDR fsp_param[1].freq_mhz= 324MHz
INFO:    dfs DDR fsp_param[2].freq_mhz= 528MHz
INFO:    dfs DDR fsp_param[3].freq_mhz= 780MHz
INFO:    Using opteed sec cpu_context!
INFO:    boot cpu mask: 0
INFO:    BL31: Initializing runtime services
WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
ERROR:   Error initializing runtime service opteed_fast
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0xa00000
INFO:    SPSR = 0x3c9

U-Boot 2023.07 (Jul 23 2023 - 13:39:45 +0000)

Model: Pine64 RK3566 SoQuartz with CM4-IO Carrier Board
DRAM:  4 GiB (effective 3.7 GiB)
PMIC:  RK8090 (on=0x40, off=0x00)
Core:  312 devices, 27 uclasses, devicetree: separate
MMC:   rockchip_sdhci_probe clk set rate fail!
mmc at fe2b0000: 1, mmc at fe2c0000: 2, mmc at fe310000: 0
Loading Environment from nowhere... OK
In:    serial at fe660000
Out:   serial at fe660000
Err:   serial at fe660000
Model: Pine64 RK3566 SoQuartz with CM4-IO Carrier Board
Net:   No ethernet found.

Hit any key to stop autoboot:  0


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