[RESEND PATCH v2] riscv: setup per-hart stack earlier

[Leo Liang]

On Sun, Jun 11, 2023 at 04:54:17PM -0700, Bo Gan wrote:
> Harts need to use per-hart stack before any function call, even if that
> function is a simple one. When the callee uses stack for register save/
> restore, especially RA, if nested call, concurrent access by multiple
> harts on the same stack will cause data-race.
> 
> This patch sets up SP before `board_init_f_alloc_reserve`. A side effect
> of this is that the memory layout has changed as the following:
> 
> +----------------+        +----------------+ <----- SPL_STACK/
> |  ......        |        |  hart 0 stack  |        SYS_INIT_SP_ADDR
> |  malloc_base   |        +----------------+
> +----------------+        |  hart 1 stack  |
> |  GD            |        +----------------+ If not SMP, N=1
> +----------------+        |  ......        |
> |  hart 0 stack  |        +----------------+
> +----------------+   ==>  |  hart N-1 stack|
> |  hart 1 stack  |        +----------------+
> +----------------+        |  ......        |
> |  ......        |        |  malloc_base   |
> +----------------+        +----------------+
> |  hart N-1 stack|        |  GD            |
> +----------------+        +----------------+
> |                |        |                |
> 
> Signed-off-by: Bo Gan <ganboing at gmail.com>
> Cc: Rick Chen <rick at andestech.com>
> Cc: Leo <ycliang at andestech.com>
> Cc: Sean Anderson <seanga2 at gmail.com>
> Cc: Bin Meng <bmeng.cn at gmail.com>
> Cc: Lukas Auer <lukas.auer at aisec.fraunhofer.de>
> Reviewed-by: Rick Chen <rick at andestech.com>
> ---
> 
> v2:
> - Fixed macro CONFIG_SYS_INIT_SP_ADDR -> SYS_INIT_SP_ADDR
> - Tested SPL with VisionFive 2 board
> ---
>  arch/riscv/cpu/start.S | 37 ++++++++++++++++++++++++-------------
>  1 file changed, 24 insertions(+), 13 deletions(-)

Reviewed-by: Leo Yu-Chi Liang <ycliang at andestech.com>