[PATCH v4 8/9] rockchip: rk3568-rock-3a: Enable PCIe and NVMe support

[Kever Yang]

On 2023/7/22 21:30, Jonas Karlman wrote:
> Add missing pinctrl and defconfig options to enable PCIe and NVMe
> support on Radxa ROCK 3 Model A.
>
> Use of pcie20m1_pins and pcie30x2m1_pins ensure IO mux selection M1.
> The following pcie_reset_h and pcie3x2_reset_h ensure GPIO func is
> restored to the perstn pin, a workaround to avoid having to define
> a new rockchip,pins.
>
> Signed-off-by: Jonas Karlman <jonas at kwiboo.se>
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever
> ---
> v4:
> - No change
>
> v3:
> - Drop now unneeded sys freeze workaround
> - Enable options for AHCI/SCSI
>
> v2:
> - Update commit message
> - Disable pcie2x1 to work around a possible sys freeze issue
>
>   arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 14 ++++++++++++++
>   configs/rock-3a-rk3568_defconfig        |  9 +++++++++
>   2 files changed, 23 insertions(+)
>
> diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
> index bbf54f888fa0..9ee7b494ee25 100644
> --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
> +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
> @@ -36,8 +36,22 @@
>   	bootph-all;
>   };
>   
> +&pcie2x1 {
> +	pinctrl-0 = <&pcie20m1_pins &pcie_reset_h>;
> +};
> +
> +&pcie3x2 {
> +	pinctrl-0 = <&pcie30x2m1_pins &pcie3x2_reset_h>;
> +};
> +
>   &pinctrl {
>   	bootph-all;
> +
> +	pcie {
> +		pcie3x2_reset_h: pcie3x2-reset-h {
> +			rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
> +		};
> +	};
>   };
>   
>   &pcfg_pull_none {
> diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
> index 753d03914d90..8e3fe0a25e1d 100644
> --- a/configs/rock-3a-rk3568_defconfig
> +++ b/configs/rock-3a-rk3568_defconfig
> @@ -22,7 +22,9 @@ CONFIG_DEBUG_UART_CLOCK=24000000
>   CONFIG_SPL_SPI_FLASH_SUPPORT=y
>   CONFIG_SPL_SPI=y
>   CONFIG_SYS_LOAD_ADDR=0xc00800
> +CONFIG_PCI=y
>   CONFIG_DEBUG_UART=y
> +CONFIG_AHCI=y
>   CONFIG_FIT=y
>   CONFIG_FIT_VERBOSE=y
>   CONFIG_SPL_FIT_SIGNATURE=y
> @@ -46,6 +48,7 @@ CONFIG_CMD_GPIO=y
>   CONFIG_CMD_GPT=y
>   CONFIG_CMD_I2C=y
>   CONFIG_CMD_MMC=y
> +CONFIG_CMD_PCI=y
>   CONFIG_CMD_USB=y
>   # CONFIG_CMD_SETEXPR is not set
>   CONFIG_CMD_PMIC=y
> @@ -56,6 +59,8 @@ CONFIG_OF_LIVE=y
>   CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
>   CONFIG_SPL_REGMAP=y
>   CONFIG_SPL_SYSCON=y
> +CONFIG_SCSI_AHCI=y
> +CONFIG_AHCI_PCI=y
>   CONFIG_SPL_CLK=y
>   CONFIG_ROCKCHIP_GPIO=y
>   CONFIG_SYS_I2C_ROCKCHIP=y
> @@ -70,6 +75,8 @@ CONFIG_SPI_FLASH_MACRONIX=y
>   CONFIG_SPI_FLASH_XTX=y
>   CONFIG_ETH_DESIGNWARE=y
>   CONFIG_GMAC_ROCKCHIP=y
> +CONFIG_NVME_PCI=y
> +CONFIG_PCIE_DW_ROCKCHIP=y
>   CONFIG_PHY_ROCKCHIP_INNO_USB2=y
>   CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
>   CONFIG_SPL_PINCTRL=y
> @@ -78,6 +85,8 @@ CONFIG_PMIC_RK8XX=y
>   CONFIG_REGULATOR_RK8XX=y
>   CONFIG_PWM_ROCKCHIP=y
>   CONFIG_SPL_RAM=y
> +CONFIG_SCSI=y
> +CONFIG_DM_SCSI=y
>   CONFIG_BAUDRATE=1500000
>   CONFIG_DEBUG_UART_SHIFT=2
>   CONFIG_SYS_NS16550_MEM32=y