[PATCH 2/4] ARM: dts: rockchip: rk3588: add support for USB 3.0 devices
Kever Yang
kever.yang at rock-chips.com
Wed Jul 26 09:35:33 CEST 2023
On 2023/5/29 18:01, Eugen Hristev wrote:
> From: Joseph Chen <chenjh at rock-chips.com>
>
> Add support for the USB 3.0 devices in rk3588:
> - USB DRD(dual role device) 3.0 #0 as usbdrd3_0 which is available in
> rk3588s
> - USB DRD(dual role device) 3.0 #1 as usbdrd3_1 which is available in
> rk3588 only
> - USB DP PHY (combo USB3.0 and DisplayPort Alt Mode ) #0 phy interface
> as usbdp_phy0
> - USB DP PHY (combo USB3.0 and DisplayPort Alt Mode ) #1 phy interface
> as usbdp_phy1
> - USB 2.0 phy #2 , the USB 3.0 device can work with this phy in USB 2.0
> mode
> - associated GRFs (general register files) for the devices.
>
> Signed-off-by: Joseph Chen <chenjh at rock-chips.com>
> [eugen.hristev at collabora.com: move nodes to right place, adapt from latest
> linux kernel]
> Signed-off-by: Eugen Hristev <eugen.hristev at collabora.com>
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>
Thanks,
- Kever
> ---
> arch/arm/dts/rk3588-u-boot.dtsi | 93 +++++++++++++++++++++++++++
> arch/arm/dts/rk3588s-u-boot.dtsi | 105 +++++++++++++++++++++++++++++++
> 2 files changed, 198 insertions(+)
>
> diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi
> index 4c8ac804d615..68b419f3abd5 100644
> --- a/arch/arm/dts/rk3588-u-boot.dtsi
> +++ b/arch/arm/dts/rk3588-u-boot.dtsi
> @@ -5,3 +5,96 @@
>
> #include "rockchip-u-boot.dtsi"
> #include "rk3588s-u-boot.dtsi"
> +
> +/ {
> + usbdrd3_1: usbdrd3_1 {
> + compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
> + clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
> + <&cru ACLK_USB3OTG1>;
> + clock-names = "ref", "suspend", "bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + usbdrd_dwc3_1: usb at fc400000 {
> + compatible = "snps,dwc3";
> + reg = <0x0 0xfc400000 0x0 0x400000>;
> + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&power RK3588_PD_USB>;
> + resets = <&cru SRST_A_USB3OTG1>;
> + reset-names = "usb3-otg";
> + dr_mode = "host";
> + phys = <&u2phy1_otg>, <&usbdp_phy1_u3>;
> + phy-names = "usb2-phy", "usb3-phy";
> + phy_type = "utmi_wide";
> + snps,dis_enblslpm_quirk;
> + snps,dis-u2-freeclk-exists-quirk;
> + snps,dis-del-phy-power-chg-quirk;
> + snps,dis-tx-ipgap-linecheck-quirk;
> + };
> + };
> +
> + usbdpphy1_grf: syscon at fd5cc000 {
> + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
> + reg = <0x0 0xfd5cc000 0x0 0x4000>;
> + };
> +
> + usb2phy1_grf: syscon at fd5d4000 {
> + compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
> + "simple-mfd";
> + reg = <0x0 0xfd5d4000 0x0 0x4000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + u2phy1: usb2-phy at 4000 {
> + compatible = "rockchip,rk3588-usb2phy";
> + reg = <0x4000 0x10>;
> + interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
> + resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
> + reset-names = "phy", "apb";
> + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
> + clock-names = "phyclk";
> + clock-output-names = "usb480m_phy1";
> + #clock-cells = <0>;
> + rockchip,usbctrl-grf = <&usb_grf>;
> + status = "disabled";
> +
> + u2phy1_otg: otg-port {
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> + };
> + };
> +
> + usbdp_phy1: phy at fed90000 {
> + compatible = "rockchip,rk3588-usbdp-phy";
> + reg = <0x0 0xfed90000 0x0 0x10000>;
> + rockchip,u2phy-grf = <&usb2phy1_grf>;
> + rockchip,usb-grf = <&usb_grf>;
> + rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
> + rockchip,vo-grf = <&vo0_grf>;
> + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
> + <&cru CLK_USBDP_PHY1_IMMORTAL>,
> + <&cru PCLK_USBDPPHY1>,
> + <&u2phy1>;
> + clock-names = "refclk", "immortal", "pclk", "utmi";
> + resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
> + <&cru SRST_USBDP_COMBO_PHY1_CMN>,
> + <&cru SRST_USBDP_COMBO_PHY1_LANE>,
> + <&cru SRST_USBDP_COMBO_PHY1_PCS>,
> + <&cru SRST_P_USBDPPHY1>;
> + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
> + status = "disabled";
> +
> + usbdp_phy1_dp: dp-port {
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> + usbdp_phy1_u3: usb3-port {
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> + };
> +};
> diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
> index 1bb3c6a9d958..acb1cfe20063 100644
> --- a/arch/arm/dts/rk3588s-u-boot.dtsi
> +++ b/arch/arm/dts/rk3588s-u-boot.dtsi
> @@ -13,6 +13,37 @@
> status = "okay";
> };
>
> + usbdrd3_0: usbdrd3_0 {
> + compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
> + clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
> + <&cru ACLK_USB3OTG0>;
> + clock-names = "ref", "suspend", "bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + usbdrd_dwc3_0: usb at fc000000 {
> + compatible = "snps,dwc3";
> + reg = <0x0 0xfc000000 0x0 0x400000>;
> + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&power RK3588_PD_USB>;
> + resets = <&cru SRST_A_USB3OTG0>;
> + reset-names = "usb3-otg";
> + dr_mode = "otg";
> + phys = <&u2phy0_otg>, <&usbdp_phy0_u3>;
> + phy-names = "usb2-phy", "usb3-phy";
> + phy_type = "utmi_wide";
> + snps,dis_enblslpm_quirk;
> + snps,dis-u1-entry-quirk;
> + snps,dis-u2-entry-quirk;
> + snps,dis-u2-freeclk-exists-quirk;
> + snps,dis-del-phy-power-chg-quirk;
> + snps,dis-tx-ipgap-linecheck-quirk;
> + quirk-skip-phy-init;
> + };
> + };
> +
> usb_host0_ehci: usb at fc800000 {
> compatible = "generic-ehci";
> reg = <0x0 0xfc800000 0x0 0x40000>;
> @@ -64,6 +95,33 @@
> reg = <0x0 0xfd5bc000 0x0 0x100>;
> };
>
> + usb2phy0_grf: syscon at fd5d0000 {
> + compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
> + "simple-mfd";
> + reg = <0x0 0xfd5d0000 0x0 0x4000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + u2phy0: usb2-phy at 0 {
> + compatible = "rockchip,rk3588-usb2phy";
> + reg = <0x0 0x10>;
> + interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
> + resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
> + reset-names = "phy", "apb";
> + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
> + clock-names = "phyclk";
> + clock-output-names = "usb480m_phy0";
> + #clock-cells = <0>;
> + rockchip,usbctrl-grf = <&usb_grf>;
> + status = "disabled";
> +
> + u2phy0_otg: otg-port {
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> + };
> + };
> +
> usb2phy2_grf: syscon at fd5d8000 {
> compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
> "simple-mfd";
> @@ -87,6 +145,17 @@
> };
> };
>
> + vo0_grf: syscon at fd5a6000 {
> + compatible = "rockchip,rk3588-vo-grf", "syscon";
> + reg = <0x0 0xfd5a6000 0x0 0x2000>;
> + clocks = <&cru PCLK_VO0GRF>;
> + };
> +
> + usb_grf: syscon at fd5ac000 {
> + compatible = "rockchip,rk3588-usb-grf", "syscon";
> + reg = <0x0 0xfd5ac000 0x0 0x4000>;
> + };
> +
> usb2phy3_grf: syscon at fd5dc000 {
> compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
> "simple-mfd";
> @@ -110,6 +179,11 @@
> };
> };
>
> + usbdpphy0_grf: syscon at fd5c8000 {
> + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
> + reg = <0x0 0xfd5c8000 0x0 0x4000>;
> + };
> +
> pcie2x1l2: pcie at fe190000 {
> compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
> #address-cells = <3>;
> @@ -180,6 +254,37 @@
> status = "disabled";
> };
>
> + usbdp_phy0: phy at fed80000 {
> + compatible = "rockchip,rk3588-usbdp-phy";
> + reg = <0x0 0xfed80000 0x0 0x10000>;
> + rockchip,u2phy-grf = <&usb2phy0_grf>;
> + rockchip,usb-grf = <&usb_grf>;
> + rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
> + rockchip,vo-grf = <&vo0_grf>;
> + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
> + <&cru CLK_USBDP_PHY0_IMMORTAL>,
> + <&cru PCLK_USBDPPHY0>,
> + <&u2phy0>;
> + clock-names = "refclk", "immortal", "pclk", "utmi";
> + resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
> + <&cru SRST_USBDP_COMBO_PHY0_CMN>,
> + <&cru SRST_USBDP_COMBO_PHY0_LANE>,
> + <&cru SRST_USBDP_COMBO_PHY0_PCS>,
> + <&cru SRST_P_USBDPPHY0>;
> + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
> + status = "disabled";
> +
> + usbdp_phy0_dp: dp-port {
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> + usbdp_phy0_u3: usb3-port {
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> + };
> +
> combphy0_ps: phy at fee00000 {
> compatible = "rockchip,rk3588-naneng-combphy";
> reg = <0x0 0xfee00000 0x0 0x100>;
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