[PATCH v2 6/7] clk: rockchip: rk3328: Handle usb480m phy clock

[Kever Yang]

On 2023/6/7 01:09, Jagan Teki wrote:
> Handle USB480M clock ID in set_rate() and set_parent()
> to allow the dt assigned-clocks and assigned-clock-parents
> work on rk3328.dtsi
>
> Cc: Lukasz Majewski <lukma at denx.de>
> Cc: Sean Anderson <seanga2 at gmail.com>
> Signed-off-by: Jagan Teki <jagan at amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever
> ---
> Changes for v2:
> - add USB480M to set_parent
>
>   drivers/clk/rockchip/clk_rk3328.c | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
> index 969b7a8581..ef97381f0e 100644
> --- a/drivers/clk/rockchip/clk_rk3328.c
> +++ b/drivers/clk/rockchip/clk_rk3328.c
> @@ -681,6 +681,7 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
>   	case ACLK_GMAC:
>   	case PCLK_GMAC:
>   	case SCLK_USB3OTG_SUSPEND:
> +	case USB480M:
>   		return 0;
>   	default:
>   		return -ENOENT;
> @@ -771,6 +772,7 @@ static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent)
>   	case SCLK_MAC2IO_EXT:
>   		return rk3328_gmac2io_ext_set_parent(clk, parent);
>   	case DCLK_LCDC:
> +	case USB480M:
>   	case SCLK_PDM:
>   	case SCLK_RTC32K:
>   	case SCLK_UART0: