[PATCH v5 6/6] mips: ls1c300: add reset support based on watchdog driver

Du Huanpeng dhu at hodcarrier.org
Wed Jul 26 14:30:27 CEST 2023


Signed-off-by: Du Huanpeng <dhu at hodcarrier.org>
---
 drivers/reset/Kconfig                     |   7 ++
 drivers/reset/Makefile                    |   1 +
 drivers/reset/reset-lsmips.c              | 118 ++++++++++++++++++++++
 include/dt-bindings/reset/ls1c300-reset.h |  36 +++++++
 4 files changed, 162 insertions(+)
 create mode 100644 drivers/reset/reset-lsmips.c
 create mode 100644 include/dt-bindings/reset/ls1c300-reset.h

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 73bbd30692..b65e2aa097 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -121,6 +121,13 @@ config RESET_SOCFPGA
 	help
 	  Support for reset controller on SoCFPGA platform.
 
+config RESET_LSMIPS
+	bool "Reset controller driver for Loongson MIPS platform"
+	depends on DM_RESET && ARCH_LSMIPS
+	default y
+	help
+	  Support for reset controller on Loongson MIPS platform.
+
 config RESET_MEDIATEK
 	bool "Reset controller driver for MediaTek SoCs"
 	depends on DM_RESET && ARCH_MEDIATEK && CLK
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index e2239a250a..5a94d9f58d 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
 obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3588.o
 obj-$(CONFIG_RESET_MESON) += reset-meson.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
+obj-$(CONFIG_RESET_LSMIPS) += reset-lsmips.o
 obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
 obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
diff --git a/drivers/reset/reset-lsmips.c b/drivers/reset/reset-lsmips.c
new file mode 100644
index 0000000000..937aac1f4c
--- /dev/null
+++ b/drivers/reset/reset-lsmips.c
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ *
+ * Author: Ryder Lee <ryder.lee at mediatek.com>
+ *	   Weijie Gao <weijie.gao at mediatek.com>
+ * Copyright (C) 2022 Du Huanpeng <dhu at hodcarrier.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <malloc.h>
+#include <dm/lists.h>
+#include <regmap.h>
+#include <reset-uclass.h>
+#include <syscon.h>
+#include <dm/device-internal.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+
+struct mediatek_reset_priv {
+	struct regmap *regmap;
+	u32 regofs;
+	u32 nr_resets;
+};
+
+int regmap_update_bits(struct regmap *map, uint offset, uint mask, uint val)
+{
+	return 0;
+}
+
+struct regmap *syscon_node_to_regmap(ofnode node)
+{
+	return NULL;
+}
+
+static int mediatek_reset_request(struct reset_ctl *reset_ctl)
+{
+	return 0;
+}
+
+static int mediatek_reset_free(struct reset_ctl *reset_ctl)
+{
+	return 0;
+}
+
+static int mediatek_reset_assert(struct reset_ctl *reset_ctl)
+{
+	struct mediatek_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	int id = reset_ctl->id;
+
+	if (id >= priv->nr_resets)
+		return -EINVAL;
+
+	return regmap_update_bits(priv->regmap,
+		priv->regofs + ((id / 32) << 2), BIT(id % 32), BIT(id % 32));
+}
+
+static int mediatek_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	struct mediatek_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	int id = reset_ctl->id;
+
+	if (id >= priv->nr_resets)
+		return -EINVAL;
+
+	return regmap_update_bits(priv->regmap,
+		priv->regofs + ((id / 32) << 2), BIT(id % 32), 0);
+}
+
+struct reset_ops mediatek_reset_ops = {
+	.request = mediatek_reset_request,
+	.rfree = mediatek_reset_free,
+	.rst_assert = mediatek_reset_assert,
+	.rst_deassert = mediatek_reset_deassert,
+};
+
+static int mediatek_reset_probe(struct udevice *dev)
+{
+	struct mediatek_reset_priv *priv = dev_get_priv(dev);
+
+	if (!priv->regofs && !priv->nr_resets)
+		return -EINVAL;
+
+	priv->regmap = syscon_node_to_regmap(dev_ofnode(dev));
+	if (IS_ERR(priv->regmap))
+		return PTR_ERR(priv->regmap);
+
+	return 0;
+}
+
+int mediatek_reset_bind(struct udevice *pdev, u32 regofs, u32 num_regs)
+{
+	struct udevice *rst_dev;
+	struct mediatek_reset_priv *priv;
+	int ret;
+
+	ret = device_bind_driver_to_node(pdev, "mediatek_reset", "reset",
+					 dev_ofnode(pdev), &rst_dev);
+	if (ret)
+		return ret;
+
+	priv = malloc(sizeof(struct mediatek_reset_priv));
+	priv->regofs = regofs;
+	priv->nr_resets = num_regs * 32;
+	dev_set_priv(rst_dev, priv);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(mediatek_reset) = {
+	.name = "loongson,shut_ctrl",
+	.id = UCLASS_RESET,
+	.probe = mediatek_reset_probe,
+	.ops = &mediatek_reset_ops,
+	.priv_auto	= sizeof(struct mediatek_reset_priv),
+};
diff --git a/include/dt-bindings/reset/ls1c300-reset.h b/include/dt-bindings/reset/ls1c300-reset.h
new file mode 100644
index 0000000000..761a6f97e0
--- /dev/null
+++ b/include/dt-bindings/reset/ls1c300-reset.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022 Du Huanpeng <dhu at hodcarrier.org>
+ */
+
+#ifndef _DT_BINDINGS_LS1C300_RESET_H_
+#define _DT_BINDINGS_LS1C300_RESET_H_
+
+#define ADC_SHUT        25
+#define SDIO_SHUT       24
+#define DMA2_SHUT       23
+#define DMA1_SHUT       22
+#define DMA0_SHUT       21
+#define SPI1_SHUT       20
+#define SPI0_SHUT       19
+#define I2C2_SHUT       18
+#define I2C1_SHUT       17
+#define I2C0_SHUT       16
+#define AC97_SHUT       15
+#define I2S_SHUT        14
+#define UART3_SHUT      13
+#define UART2_SHUT      12
+#define UART1_SHUT      11
+#define UART0_SHUT      10
+#define CAN1_SHUT       9
+#define CAN0_SHUT       8
+#define ECC_SHUT        7
+#define MAC_SHUT        6
+#define USBHOST_SHUT    5
+#define USBOTG_SHUT     4
+#define SDRAM_SHUT      3
+#define SRAM_SHUT       2
+#define CAM_SHUT        1
+#define LCD_SHUT        0
+
+#endif  /* _DT_BINDINGS_LS1C300_RESET_H_*/
-- 
2.34.1



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