[PATCH v5 23/46] pci: Allow the video BIOS to work in SPL with QEMU

[Simon Glass]

Hi Bin,

On Mon, 17 Jul 2023 at 00:20, Bin Meng <bmeng.cn at gmail.com> wrote:
>
> Hi Simon,
>
> On Sun, Jul 16, 2023 at 11:39 AM Simon Glass <sjg at chromium.org> wrote:
> >
> > QEMU emulates two common machines (Q35 and i440fx) which use mapping to
> > determine whether RAM is present below 1MB. In order to copy the video
> > BIOS to c0000 we need to flip this mapping over to RAM. This does not
> > happen automatically until SPL has finished running.
> >
> > Switch in RAM at these address so that the video BIOS can be loaded and
> > run.
> >
> > Create a generic qemu.h header to avoid having to #ifdef the header in
> > pci_rom.c
> >
> > Signed-off-by: Simon Glass <sjg at chromium.org>
> > ---
> >
> > Changes in v5:
> > - Use the existing QEMU code instead
> >
> >  arch/x86/cpu/qemu/qemu.c |  5 +++--
> >  drivers/pci/pci_rom.c    |  5 +++++
> >  include/qemu.h           | 14 ++++++++++++++
> >  3 files changed, 22 insertions(+), 2 deletions(-)
> >  create mode 100644 include/qemu.h
> >
> > diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
> > index 274978c023b6..a84d2aceda3c 100644
> > --- a/arch/x86/cpu/qemu/qemu.c
> > +++ b/arch/x86/cpu/qemu/qemu.c
> > @@ -7,6 +7,7 @@
> >  #include <cpu_func.h>
> >  #include <init.h>
> >  #include <pci.h>
> > +#include <qemu.h>
> >  #include <qfw.h>
> >  #include <dm/platdata.h>
> >  #include <asm/irq.h>
> > @@ -48,7 +49,7 @@ static void enable_pm_ich9(void)
> >         pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
> >  }
> >
> > -static void qemu_chipset_init(void)
> > +void qemu_x86_chipset_init(void)
> >  {
> >         u16 device, xbcs;
> >         int pam, i;
> > @@ -119,7 +120,7 @@ int print_cpuinfo(void)
> >
> >  int arch_early_init_r(void)
> >  {
> > -       qemu_chipset_init();
> > +       qemu_x86_chipset_init();
> >
> >         return 0;
> >  }
> > diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
> > index f0dfe6314907..447957fb23aa 100644
> > --- a/drivers/pci/pci_rom.c
> > +++ b/drivers/pci/pci_rom.c
> > @@ -34,6 +34,7 @@
> >  #include <malloc.h>
> >  #include <pci.h>
> >  #include <pci_rom.h>
> > +#include <qemu.h>
> >  #include <vesa.h>
> >  #include <video.h>
> >  #include <acpi/acpi_s3.h>
> > @@ -185,6 +186,10 @@ static int pci_rom_load(struct pci_rom_header *rom_header,
> >                 return -ENOMEM;
> >         *allocedp = true;
> >  #endif
> > +       /* QEMU hacks */
> > +       if (IS_ENABLED(CONFIG_X86) && IS_ENABLED(CONFIG_QEMU))
> > +               qemu_x86_chipset_init();
> > +
>
> Maybe I did not say it clearly in the previous version. I think we
> should avoid polluting the generic pci_rom.c codes.
>
> First of all, these are not QEMU hacks, but are required operations
> against a specific Intel chipset. QEMU just emulates the real hardware
> behavior.
>
> Second, we should update x86 SPL codes to call qemu_chipset_init() for
> QEMU x86_64.

OK I understand now. I sent a new series that includes a new patch\.

Regards,
Simon