[PATCH] ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOM

[Patrick DELAUNAY]

Hi,

On 7/27/23 00:45, Marek Vasut wrote:
> The DHCOM SoM has two options for supplying ETHRX clock to the DWMAC
> block and PHY. Either (1) ETHCK_K generates 50 MHz clock on ETH_CLK
> pad for the PHY and the same 50 MHz clock are fed back to ETHRX via
> internal eth_clk_fb clock connection OR (2) ETH_CLK is not used at
> all, MCO2 generates 50 MHz clock on MCO2 output pad for the PHY and
> the same MCO2 clock are fed back into ETHRX via ETH_RX_CLK input pad
> using external pad-to-pad connection.
>
> Option (1) has two downsides. ETHCK_K is supplied directly from either
> PLL3_Q or PLL4_P, hence the PLL output is limited to exactly 50 MHz and
> since the same PLL output is also used to supply SDMMC blocks, the
> performance of SD and eMMC access is affected. The second downside is
> that using this option, the EMI of the SoM is higher.
>
> Option (2) solves both of those problems, so implement it here. In this
> case, the PLL4_P is no longer limited and can be operated faster, at
> 100 MHz, which improves SDMMC performance (read performance is improved
> from ~41 MiB/s to ~57 MiB/s with dd if=/dev/mmcblk1 of=/dev/null bs=64M
> count=1). The EMI interference also decreases.
>
> Ported from Linux kernel commit
> 73ab99aad50cd ("ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOM")
>
> Signed-off-by: Marek Vasut <marex at denx.de>
> ---
> Cc: Patrice Chotard <patrice.chotard at foss.st.com>
> Cc: Patrick Delaunay <patrick.delaunay at foss.st.com>
> Cc: u-boot at dh-electronics.com
> Cc: uboot-stm32 at st-md-mailman.stormreply.com
> ---
>   arch/arm/dts/stm32mp15xx-dhcom-som.dtsi | 22 ++++++++++++++++++----
>   1 file changed, 18 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi
> index 83e2c87713f..238a611192e 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi
> +++ b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi
> @@ -118,13 +118,12 @@
>   
>   &ethernet0 {
>   	status = "okay";
> -	pinctrl-0 = <&ethernet0_rmii_pins_a>;
> -	pinctrl-1 = <&ethernet0_rmii_sleep_pins_a>;
> +	pinctrl-0 = <&ethernet0_rmii_pins_c &mco2_pins_a>;
> +	pinctrl-1 = <&ethernet0_rmii_sleep_pins_c &mco2_sleep_pins_a>;
>   	pinctrl-names = "default", "sleep";
>   	phy-mode = "rmii";
>   	max-speed = <100>;
>   	phy-handle = <&phy0>;
> -	st,eth-ref-clk-sel;
>   
>   	mdio0 {
>   		#address-cells = <1>;
> @@ -136,7 +135,7 @@
>   			/* LAN8710Ai */
>   			compatible = "ethernet-phy-id0007.c0f0",
>   				     "ethernet-phy-ieee802.3-c22";
> -			clocks = <&rcc ETHCK_K>;
> +			clocks = <&rcc CK_MCO2>;
>   			reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
>   			reset-assert-us = <500>;
>   			reset-deassert-us = <500>;
> @@ -446,6 +445,21 @@
>   	};
>   };
>   
> +&rcc {
> +	/* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */
> +	clocks = <&rcc CK_MCO2>;
> +	clock-names = "ETH_RX_CLK/ETH_REF_CLK";
> +
> +	/*
> +	 * Set PLL4P output to 100 MHz to supply SDMMC with faster clock,
> +	 * set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2,
> +	 * so that MCO2 behaves as a divider for the ETHRX clock here.
> +	 */
> +	assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>;
> +	assigned-clock-parents = <&rcc PLL4_P>;
> +	assigned-clock-rates = <50000000>, <100000000>;
> +};
> +
>   &rng1 {
>   	status = "okay";
>   };


Reviewed-by: Patrick Delaunay <patrick.delaunay at foss.st.com>

ok for device tree alignment


but this MCO2 assignment if not functional in U-Boot clock driver

- set_parent() => is not defined

- set_rate() => is only supported for a limited number of clock, PLL4_Q 
for example


but OK as the MCO2 is already configured in the clock tree directly in 
U-Boot SPL:

./arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi

&rcc {
     st,clksrc = <
...
         CLK_MCO2_PLL4P
     >;

     st,clkdiv = <
...
         1 /*MCO2*/
     >;


Thanks
Patrick