[PATCH V4 9/9] doc: board: ti: am62x_sk: Add A53 SPL DDR layout

[Tom Rini]

On Fri, Jun 16, 2023 at 04:22:38PM +0530, Nikhil M Jain wrote:
> To understand usage of DDR in A53 SPL stage, add a table showing region
> and space used by major components of SPL.
> 
> Signed-off-by: Nikhil M Jain <n-jain1 at ti.com>
> ---
> V4(patch introduced):
> - Document A53 SPL DDR memory layout.
> 
>  doc/board/ti/am62x_sk.rst | 53 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 53 insertions(+)
> 
> diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst
> index 27d7b527c6..ac40f8d3c4 100644
> --- a/doc/board/ti/am62x_sk.rst
> +++ b/doc/board/ti/am62x_sk.rst
> @@ -230,6 +230,59 @@ Image formats:
>                  | +-------------------+ |
>                  +-----------------------+
>  
> +A53 SPL DDR Memory Layout
> +-------------------------
> +
> +This provides an overview memory usage in A53 SPL stage.
> +
> + .. code-block:: text

The correct table format to use is in the previous section.

-- 
Tom
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