[PATCH V4 9/9] doc: board: ti: am62x_sk: Add A53 SPL DDR layout
Nikhil M Jain
n-jain1 at ti.com
Mon Jun 19 10:06:16 CEST 2023
Hi Tom,
On 16/06/23 20:24, Tom Rini wrote:
> On Fri, Jun 16, 2023 at 04:22:38PM +0530, Nikhil M Jain wrote:
>> To understand usage of DDR in A53 SPL stage, add a table showing region
>> and space used by major components of SPL.
>>
>> Signed-off-by: Nikhil M Jain <n-jain1 at ti.com>
>> ---
>> V4(patch introduced):
>> - Document A53 SPL DDR memory layout.
>>
>> doc/board/ti/am62x_sk.rst | 53 +++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 53 insertions(+)
>>
>> diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst
>> index 27d7b527c6..ac40f8d3c4 100644
>> --- a/doc/board/ti/am62x_sk.rst
>> +++ b/doc/board/ti/am62x_sk.rst
>> @@ -230,6 +230,59 @@ Image formats:
>> | +-------------------+ |
>> +-----------------------+
>>
>> +A53 SPL DDR Memory Layout
>> +-------------------------
>> +
>> +This provides an overview memory usage in A53 SPL stage.
>> +
>> + .. code-block:: text
>
> The correct table format to use is in the previous section.
>
+---------------------+0x80000000
| Empty 512 KB |
| |
+---------------------+0x80080000
| Text Base |
| 352 KB |
| |
+---------------------+0x800D8000
| Empty 1.1MB |
| |
+---------------------+0x80200000
| |
| |
| |
| BMP Image Load |
| |
| 9.4 MB |
| |
| |
| |
| |
| |
| |
+---------------------+0x80B77660
| Stack 2KB |
+---------------------+0x80B77e60
| GD 416 Bytes |
+---------------------+0x80B78000
| |
| Malloc 352KB |
+---------------------+0x80B80000
| |
| Empty 1 MB |
| |
+---------------------+0x80C80000
| BSS 512 KB |
| |
+---------------------+0x80D00000
| Blobs 1KB |
+---------------------+0x80D00400
| |
| Empty 2.999MB |
| |
| |
+---------------------+FIT Image load address 0x81000000
Is this the right format?
Thank you,
Nikhil
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