Pull Request / Patch: Enable Usage of ECC with DDR on AM654x

[Roytburd, Benjamin]

Nishanth,

Agreed, this is very expensive for boot time, I could probably add a comment to address this. But I believe it is better to have this option than not, as I struggled to figure out that I even needed to prime ECC when I enabled it.

What is the strategy for TODOs with U-boot? DMA would probably be the best option here instead of memset / for loop, but I do not have that implemented yet. I could submit it in a future patch.

Thanks,
Ben

________________________________
From: Nishanth Menon <nm at ti.com>
Sent: Friday, May 5, 2023, 8:51 AM
To: Tom Rini <trini at konsulko.com>
Cc: Roytburd, Benjamin <roytburd at msu.edu>; u-boot at lists.denx.de <u-boot at lists.denx.de>
Subject: Re: Pull Request / Patch: Enable Usage of ECC with DDR on AM654x

Benjamin,

On 21:59-20230504, Tom Rini wrote:
> On Thu, May 04, 2023 at 12:47:29PM +0000, Roytburd, Benjamin wrote:
> o
> > Hello,
> >
> > Recently, when working with the AM65x_GP_EVM development board, I found that the U-boot source code (specifically the SPL), does not properly initialize the DDRSS ram drivers for the AM6548. There are missing register writes that are required from DDR to function with ECC on.
> >
> > I validated this by comparing what U-boot source code does to Texas Instrument DDR test scripts (known as GEL scripts), and these GEL scripts could properly initialize DDR with ECC while U-boot could not, this is due to the missing register writes. The changes are shown here in this pull request: https://urldefense.com/v3/__https://github.com/u-boot/u-boot/pull/289__;!!HXCxUKc!1GAn_RygP2YfrkD6PwS6XTNm0d0yft7cgoHX9LO-jxrIJcpcUjzuaMlV38MkwMU22dIsmw$  (made just to check CI).
> >
> > Should I submit a patch for this? I have not contributed to U-boot before and would like to know if such a change would be accepted, or even reviewed, as a submission.
>
> Yes, please submit a patch for it and cc the people that the
> scripts/get_maintainer.pl script suggests, thanks!

While you follow the formal submission process, I happened to glance
at your patch and could'nt help but comment, because we have enabled
ECC in our platforms (off tree) - Time taken to do ECC priming is the
hardest topic.. memset (essentially what you did) is probably the most
easiest way to attempt, BUT, it is very very expensive to boot time.
That is not acceptable for real products. We have struggled with the
same with various options proposed.

Please note that when you do submit the patches, you want to keep
in mind that it is not just one board that the DDR driver supports
- there are lots of boards that support this + an ecosystem of
tools such as the DDR configuration tool that spits out the DDR
configuration.

All of these should be factored into your patches when you post.
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D