Pull Request / Patch: Enable Usage of ECC with DDR on AM654x

Nishanth Menon nm at ti.com
Wed May 17 20:30:23 CEST 2023

On 14:23-20230505, Roytburd, Benjamin wrote:
> Nishanth,

Gentle reminder: Please do not top post  - email etiquette in upstream mailing
as well as please do not use flowed formatting. See [1] (I use neomutt
personally with 70 char line break)

> Agreed, this is very expensive for boot time, I could probably add a comment
> to address this. But I believe it is better to have this option than not, as
> I struggled to figure out that I even needed to prime ECC when I enabled it.
> What is the strategy for TODOs with U-boot? DMA would probably be the best
> option here instead of memset / for loop, but I do not have that implemented
> yet. I could submit it in a future patch.

Remember what I mentioned in my response: there are quite a few other
folks also using the SoC support and evm. They would rather not want
to see the increase in boot time if we merge such a change. I don't see
a reasonable alternative without using DMA to prime effectively.

Also, is blindly enabling ECC across the DDR effective or creating
other problems? Access latencies are increased (since incoming and
outgoing bursts need to be checked against checksum) or should we
scheme something with a range?


[1] https://www.kernel.org/doc/html/v6.3/process/email-clients.html
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

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