[PATCH v2] arm64: zynqmp: Comment all smmu entries
Michal Simek
michal.simek at amd.com
Tue Nov 7 13:38:15 CET 2023
On 11/1/23 09:01, Michal Simek wrote:
> SMMU is disabled by default and not all masters can be enabled at the same
> time because of limited number of entries. That's why comment all iommu
> properties but keep them for reference in DT. In XEN case they should be
> added back and Xen should have SMMU enabled by default.
> Also add IDs for DP and DPDMA.
>
> Signed-off-by: Michal Simek <michal.simek at amd.com>
> ---
>
> Changes in v2:
> - add missing one for DPDMA
> - update commit message to cover DP and DPDMA
>
> arch/arm/dts/zynqmp.dtsi | 59 ++++++++++++++++++++--------------------
> 1 file changed, 30 insertions(+), 29 deletions(-)
>
> diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
> index 2253e773d386..66d53359d83d 100644
> --- a/arch/arm/dts/zynqmp.dtsi
> +++ b/arch/arm/dts/zynqmp.dtsi
> @@ -339,7 +339,7 @@
> clock-names = "clk_main", "clk_apb";
> #dma-cells = <1>;
> xlnx,bus-width = <128>;
> - iommus = <&smmu 0x14e8>;
> + /* iommus = <&smmu 0x14e8>; */
> power-domains = <&zynqmp_firmware PD_GDMA>;
> };
>
> @@ -352,7 +352,7 @@
> clock-names = "clk_main", "clk_apb";
> #dma-cells = <1>;
> xlnx,bus-width = <128>;
> - iommus = <&smmu 0x14e9>;
> + /* iommus = <&smmu 0x14e9>; */
> power-domains = <&zynqmp_firmware PD_GDMA>;
> };
>
> @@ -365,7 +365,7 @@
> clock-names = "clk_main", "clk_apb";
> #dma-cells = <1>;
> xlnx,bus-width = <128>;
> - iommus = <&smmu 0x14ea>;
> + /* iommus = <&smmu 0x14ea>; */
> power-domains = <&zynqmp_firmware PD_GDMA>;
> };
>
> @@ -378,7 +378,7 @@
> clock-names = "clk_main", "clk_apb";
> #dma-cells = <1>;
> xlnx,bus-width = <128>;
> - iommus = <&smmu 0x14eb>;
> + /* iommus = <&smmu 0x14eb>; */
> power-domains = <&zynqmp_firmware PD_GDMA>;
> };
>
> @@ -391,7 +391,7 @@
> clock-names = "clk_main", "clk_apb";
> #dma-cells = <1>;
> xlnx,bus-width = <128>;
> - iommus = <&smmu 0x14ec>;
> + /* iommus = <&smmu 0x14ec>; */
> power-domains = <&zynqmp_firmware PD_GDMA>;
> };
>
> @@ -404,7 +404,7 @@
> clock-names = "clk_main", "clk_apb";
> #dma-cells = <1>;
> xlnx,bus-width = <128>;
> - iommus = <&smmu 0x14ed>;
> + /* iommus = <&smmu 0x14ed>; */
> power-domains = <&zynqmp_firmware PD_GDMA>;
> };
>
> @@ -417,7 +417,7 @@
> clock-names = "clk_main", "clk_apb";
> #dma-cells = <1>;
> xlnx,bus-width = <128>;
> - iommus = <&smmu 0x14ee>;
> + /* iommus = <&smmu 0x14ee>; */
> power-domains = <&zynqmp_firmware PD_GDMA>;
> };
>
> @@ -430,7 +430,7 @@
> clock-names = "clk_main", "clk_apb";
> #dma-cells = <1>;
> xlnx,bus-width = <128>;
> - iommus = <&smmu 0x14ef>;
> + /* iommus = <&smmu 0x14ef>; */
> power-domains = <&zynqmp_firmware PD_GDMA>;
> };
>
> @@ -475,7 +475,7 @@
> clock-names = "clk_main", "clk_apb";
> #dma-cells = <1>;
> xlnx,bus-width = <64>;
> - iommus = <&smmu 0x868>;
> + /* iommus = <&smmu 0x868>; */
> power-domains = <&zynqmp_firmware PD_ADMA>;
> };
>
> @@ -488,7 +488,7 @@
> clock-names = "clk_main", "clk_apb";
> #dma-cells = <1>;
> xlnx,bus-width = <64>;
> - iommus = <&smmu 0x869>;
> + /* iommus = <&smmu 0x869>; */
> power-domains = <&zynqmp_firmware PD_ADMA>;
> };
>
> @@ -501,7 +501,7 @@
> clock-names = "clk_main", "clk_apb";
> #dma-cells = <1>;
> xlnx,bus-width = <64>;
> - iommus = <&smmu 0x86a>;
> + /* iommus = <&smmu 0x86a>; */
> power-domains = <&zynqmp_firmware PD_ADMA>;
> };
>
> @@ -514,7 +514,7 @@
> clock-names = "clk_main", "clk_apb";
> #dma-cells = <1>;
> xlnx,bus-width = <64>;
> - iommus = <&smmu 0x86b>;
> + /* iommus = <&smmu 0x86b>; */
> power-domains = <&zynqmp_firmware PD_ADMA>;
> };
>
> @@ -527,7 +527,7 @@
> clock-names = "clk_main", "clk_apb";
> #dma-cells = <1>;
> xlnx,bus-width = <64>;
> - iommus = <&smmu 0x86c>;
> + /* iommus = <&smmu 0x86c>; */
> power-domains = <&zynqmp_firmware PD_ADMA>;
> };
>
> @@ -540,7 +540,7 @@
> clock-names = "clk_main", "clk_apb";
> #dma-cells = <1>;
> xlnx,bus-width = <64>;
> - iommus = <&smmu 0x86d>;
> + /* iommus = <&smmu 0x86d>; */
> power-domains = <&zynqmp_firmware PD_ADMA>;
> };
>
> @@ -553,7 +553,7 @@
> clock-names = "clk_main", "clk_apb";
> #dma-cells = <1>;
> xlnx,bus-width = <64>;
> - iommus = <&smmu 0x86e>;
> + /* iommus = <&smmu 0x86e>; */
> power-domains = <&zynqmp_firmware PD_ADMA>;
> };
>
> @@ -566,7 +566,7 @@
> clock-names = "clk_main", "clk_apb";
> #dma-cells = <1>;
> xlnx,bus-width = <64>;
> - iommus = <&smmu 0x86f>;
> + /* iommus = <&smmu 0x86f>; */
> power-domains = <&zynqmp_firmware PD_ADMA>;
> };
>
> @@ -586,7 +586,7 @@
> interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> - iommus = <&smmu 0x872>;
> + /* iommus = <&smmu 0x872>; */
> power-domains = <&zynqmp_firmware PD_NAND>;
> };
>
> @@ -598,7 +598,7 @@
> <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> reg = <0x0 0xff0b0000 0x0 0x1000>;
> clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
> - iommus = <&smmu 0x874>;
> + /* iommus = <&smmu 0x874>; */
> power-domains = <&zynqmp_firmware PD_ETH_0>;
> resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
> reset-names = "gem0_rst";
> @@ -612,7 +612,7 @@
> <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> reg = <0x0 0xff0c0000 0x0 0x1000>;
> clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
> - iommus = <&smmu 0x875>;
> + /* iommus = <&smmu 0x875>; */
> power-domains = <&zynqmp_firmware PD_ETH_1>;
> resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
> reset-names = "gem1_rst";
> @@ -626,7 +626,7 @@
> <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> reg = <0x0 0xff0d0000 0x0 0x1000>;
> clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
> - iommus = <&smmu 0x876>;
> + /* iommus = <&smmu 0x876>; */
> power-domains = <&zynqmp_firmware PD_ETH_2>;
> resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
> reset-names = "gem2_rst";
> @@ -640,7 +640,7 @@
> <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
> reg = <0x0 0xff0e0000 0x0 0x1000>;
> clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
> - iommus = <&smmu 0x877>;
> + /* iommus = <&smmu 0x877>; */
> power-domains = <&zynqmp_firmware PD_ETH_3>;
> resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;
> reset-names = "gem3_rst";
> @@ -719,7 +719,7 @@
> <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
> <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
> <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
> - iommus = <&smmu 0x4d0>;
> + /* iommus = <&smmu 0x4d0>; */
> power-domains = <&zynqmp_firmware PD_PCIE>;
> pcie_intc: legacy-interrupt-controller {
> interrupt-controller;
> @@ -740,7 +740,7 @@
> <0x0 0xc0000000 0x0 0x8000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> - iommus = <&smmu 0x873>;
> + /* iommus = <&smmu 0x873>; */
> power-domains = <&zynqmp_firmware PD_QSPI>;
> };
>
> @@ -772,8 +772,7 @@
> interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> power-domains = <&zynqmp_firmware PD_SATA>;
> resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
> - iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
> - <&smmu 0x4c2>, <&smmu 0x4c3>;
> + /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */
> /* dma-coherent; */
> };
>
> @@ -785,7 +784,7 @@
> interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> reg = <0x0 0xff160000 0x0 0x1000>;
> clock-names = "clk_xin", "clk_ahb";
> - iommus = <&smmu 0x870>;
> + /* iommus = <&smmu 0x870>; */
> #clock-cells = <1>;
> clock-output-names = "clk_out_sd0", "clk_in_sd0";
> power-domains = <&zynqmp_firmware PD_SD_0>;
> @@ -800,7 +799,7 @@
> interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> reg = <0x0 0xff170000 0x0 0x1000>;
> clock-names = "clk_xin", "clk_ahb";
> - iommus = <&smmu 0x871>;
> + /* iommus = <&smmu 0x871>; */
> #clock-cells = <1>;
> clock-output-names = "clk_out_sd1", "clk_in_sd1";
> power-domains = <&zynqmp_firmware PD_SD_1>;
> @@ -951,7 +950,7 @@
> interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> - iommus = <&smmu 0x860>;
> + /* iommus = <&smmu 0x860>; */
> snps,quirk-frame-length-adjustment = <0x20>;
> clock-names = "ref";
> snps,enable_guctl1_ipd_quirk;
> @@ -983,7 +982,7 @@
> interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> - iommus = <&smmu 0x861>;
> + /* iommus = <&smmu 0x861>; */
> snps,quirk-frame-length-adjustment = <0x20>;
> clock-names = "ref";
> snps,enable_guctl1_ipd_quirk;
> @@ -1043,6 +1042,7 @@
> interrupt-parent = <&gic>;
> clock-names = "axi_clk";
> power-domains = <&zynqmp_firmware PD_DP>;
> + /* iommus = <&smmu 0xce4>; */
> #dma-cells = <1>;
> };
>
> @@ -1057,6 +1057,7 @@
> reg-names = "dp", "blend", "av_buf", "aud";
> interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-parent = <&gic>;
> + /* iommus = <&smmu 0xce3>; */
> clock-names = "dp_apb_clk", "dp_aud_clk",
> "dp_vtc_pixel_clk_in";
> power-domains = <&zynqmp_firmware PD_DP>;
applied.
M
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