[PATCH v6 3/4] riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT

[Leo Liang]

On Fri, Aug 25, 2023 at 12:25:20AM +0800, Shengyu Qu wrote:
> Starfive JH7110 needs to clear L2 LIM to zero before use or ECC error
> would be triggered. Currently, we use DDR ram for SPL malloc arena on
> Visionfive 2 board in defconfig, but it's also possible to use L2 LIM as
> SPL malloc arena. To avoid triggering ECC error in this scenario, we
> imply SPL_SYS_MALLOC_CLEAR_ON_INIT as default.
> 
> Signed-off-by: Bo Gan <ganboing at gmail.com>
> Signed-off-by: Shengyu Qu <wiagn233 at outlook.com>
> ---
>  arch/riscv/cpu/jh7110/Kconfig | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Leo Yu-Chi Liang <ycliang at andestech.com>