[PATCH v2 2/9] x86: broadwell: Show the memory delay
Simon Glass
sjg at chromium.org
Thu Sep 7 17:58:14 CEST 2023
Samus only takes 7 seconds but it is long enough to think it has hung. Add
a message about what it is doing, similar to the approach on coral.
Signed-off-by: Simon Glass <sjg at chromium.org>
Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
---
(no changes since v1)
arch/x86/cpu/intel_common/mrc.c | 18 +++++++++++++++++-
arch/x86/dts/chromebook_samus.dts | 1 +
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c
index 56cc253831aa..ff959d1bd8d8 100644
--- a/arch/x86/cpu/intel_common/mrc.c
+++ b/arch/x86/cpu/intel_common/mrc.c
@@ -9,6 +9,7 @@
#include <dm.h>
#include <init.h>
#include <log.h>
+#include <spl.h>
#include <syscon.h>
#include <asm/cpu.h>
#include <asm/global_data.h>
@@ -251,13 +252,28 @@ static int sdram_initialise(struct udevice *dev, struct udevice *me_dev,
int mrc_common_init(struct udevice *dev, void *pei_data, bool use_asm_linkage)
{
struct udevice *me_dev;
- int ret;
+ int ret, delay;
ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
if (ret)
return ret;
+ delay = dev_read_u32_default(dev, "fspm,training-delay", 0);
+ if (spl_phase() == PHASE_SPL) {
+ if (delay)
+ printf("SDRAM training (%d seconds)...", delay);
+ else
+ log_debug("SDRAM init...");
+ } else {
+ if (delay)
+ printf("(%d seconds)...", delay);
+ }
+
ret = sdram_initialise(dev, me_dev, pei_data, use_asm_linkage);
+ if (delay)
+ printf("done\n");
+ else
+ log_debug("done\n");
if (ret)
return ret;
quick_ram_check();
diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts
index 96705ceed074..ddff277046a4 100644
--- a/arch/x86/dts/chromebook_samus.dts
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -266,6 +266,7 @@
board-id-gpios = <&gpio_c 5 0>, <&gpio_c 4 0>,
<&gpio_c 3 0>, <&gpio_c 1 0>;
bootph-all;
+ fspm,training-delay = <7>;
spd {
#address-cells = <1>;
#size-cells = <0>;
--
2.42.0.283.g2d96d420d3-goog
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