[RFT PATCH 2/2] mmc: meson-gx: set 270 core phase during the identification

[Jerome Brunet]

It has been reported that some devices have problems with a 180 degree
core phase. Setting 270 helped some of these devices. Other continue to
struggle (while it works fine with 180 in Linux ... :sigh:)

Poking around the HW, it seems that setting a 270 core phase during the
identification, then using 180 for the rest of the operations, helps the
device operate correctly.

Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
---
 drivers/mmc/meson_gx_mmc.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
index c6168792cbae..284be2b9dca4 100644
--- a/drivers/mmc/meson_gx_mmc.c
+++ b/drivers/mmc/meson_gx_mmc.c
@@ -54,9 +54,14 @@ static void meson_mmc_config_clock(struct mmc *mmc)
 
 	/* Clk always on */
 	meson_mmc_clk |= pdata->version->clk_always_on;
-	meson_mmc_clk |= CLK_CO_PHASE_180;
 	meson_mmc_clk |= CLK_TX_PHASE_000;
 
+	/* Core phase according to mode */
+	if (mmc->selected_mode == MMC_LEGACY)
+		meson_mmc_clk |= CLK_CO_PHASE_270;
+	else
+		meson_mmc_clk |= CLK_CO_PHASE_180;
+
 	/* 1GHz / CLK_MAX_DIV = 15,9 MHz */
 	if (mmc->clock > 16000000) {
 		clk = SD_EMMC_CLKSRC_DIV2;
-- 
2.40.1