[PATCH 19/20] clk: renesas: Synchronize R8A774C0 RZ/G2E clock tables with Linux 6.5.3

[Marek Vasut]

Synchronize R8A774C0 RZ/G2E clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut <marek.vasut+renesas at mailbox.org>
---
 drivers/clk/renesas/r8a774c0-cpg-mssr.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index 802a9c0b119..4768ceb0fa6 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -52,7 +52,7 @@ enum clk_ids {
 	MOD_CLK_BASE
 };
 
-static const struct cpg_core_clk r8a774c0_core_clks[] = {
+static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
 	/* External Clock Inputs */
 	DEF_INPUT("extal",     CLK_EXTAL),
 
@@ -131,7 +131,7 @@ static const struct cpg_core_clk r8a774c0_core_clks[] = {
 	DEF_GEN3_RCKSEL("r",   R8A774C0_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
 };
 
-static const struct mssr_mod_clk r8a774c0_mod_clks[] = {
+static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
 	DEF_MOD("tmu4",			 121,	R8A774C0_CLK_S0D6C),
 	DEF_MOD("tmu3",			 122,	R8A774C0_CLK_S3D2C),
 	DEF_MOD("tmu2",			 123,	R8A774C0_CLK_S3D2C),
@@ -259,7 +259,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] = {
  */
 #define CPG_PLL_CONFIG_INDEX(md)	(((md) & BIT(19)) >> 19)
 
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
 	/* EXTAL div	PLL1 mult/div	PLL3 mult/div */
 	{ 1,		100,	3,	100,	3,	},
 	{ 1,		100,	3,	 58,	3,	},
-- 
2.40.1