[PATCH v4 06/20] x86: coreboot: Look for DBG2 UART in SPL too

[Bin Meng]

On Thu, Aug 24, 2023 at 5:11 AM Simon Glass <sjg at chromium.org> wrote:
>
> If coreboot does not set up sysinfo for the UART, SPL currently hangs.
> Use the DBG2 teechnique there as well. This allows coreboot64 to boot from

typo: technique

> coreboot even if the console info is missing from sysinfo
>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
>
> (no changes since v1)
>
>  configs/coreboot64_defconfig | 1 +
>  drivers/serial/Kconfig       | 2 +-
>  2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig
> index 5623197f6be..e8165961c19 100644
> --- a/configs/coreboot64_defconfig
> +++ b/configs/coreboot64_defconfig
> @@ -54,4 +54,5 @@ CONFIG_SYS_64BIT_LBA=y
>  CONFIG_SOUND=y
>  CONFIG_SOUND_I8254=y
>  CONFIG_CONSOLE_SCROLL_LINES=5
> +CONFIG_SPL_ACPI=y
>  # CONFIG_GZIP is not set
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index 7ca42df6a7e..27b4b9d9650 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -672,7 +672,7 @@ config COREBOOT_SERIAL
>  config COREBOOT_SERIAL_FROM_DBG2
>         bool "Obtain UART from ACPI tables"
>         depends on COREBOOT_SERIAL
> -       default y if !SPL
> +       default y
>         help
>           Select this to try to find a DBG2 record in the ACPI tables, in the
>           event that coreboot does not provide information about the UART in the
> --

Reviewed-by: Bin Meng <bmeng.cn at gmail.com>