[PATCH 4/5] arm64: dts: imx8mp: Drop i.MX8MP DHCOM rev.100 PHY address workaround from PDK3 DT

[Marek Vasut]

In case the i.MX8MP DHCOM rev.100 has been populated on the PDK3
carrier board, the on-SoM PHY PHYAD1 signal has been pulled high
by the carrier board and changed the PHY MDIO address from 5 to 7.
This has been fixed on production rev.200 SoM by additional buffer
on the SoM PHYAD/LED signals, remove the workaround.

Signed-off-by: Marek Vasut <marex at denx.de>
---
Cc: "NXP i.MX U-Boot Team" <uboot-imx at nxp.com>
Cc: Algapally Santosh Sagar <santoshsagar.algapally at amd.com>
Cc: Fabio Estevam <festevam at gmail.com>
Cc: Mayuresh Chitale <mchitale at ventanamicro.com>
Cc: Oleksandr Suvorov <oleksandr.suvorov at foundries.io>
Cc: Ovidiu Panait <ovpanait at gmail.com>
Cc: Roger Quadros <rogerq at kernel.org>
Cc: Simon Glass <sjg at chromium.org>
Cc: Stefano Babic <sbabic at denx.de>
Cc: u-boot at dh-electronics.com
---
 arch/arm/dts/imx8mp-dhcom-pdk3.dts | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/dts/imx8mp-dhcom-pdk3.dts b/arch/arm/dts/imx8mp-dhcom-pdk3.dts
index c5f0607f43b..867d238f2b5 100644
--- a/arch/arm/dts/imx8mp-dhcom-pdk3.dts
+++ b/arch/arm/dts/imx8mp-dhcom-pdk3.dts
@@ -227,10 +227,6 @@
 	};
 };
 
-&ethphy0g {
-	reg = <7>;
-};
-
 &fec {	/* Second ethernet */
 	pinctrl-0 = <&pinctrl_fec_rgmii>;
 	phy-handle = <&ethphypdk>;
-- 
2.40.1