[PATCH 06/14] arm64: zynqmp: Fix Siva's email address format

Michal Simek michal.simek at amd.com
Fri Sep 22 12:35:35 CEST 2023


Some patches didn't have his full name and also there was one more ">" at
the end of email address. That's why correct both of these issues.

Fixes: 174d728471d5 ("arm64: zynqmp: Switch to amd.com emails")
Signed-off-by: Michal Simek <michal.simek at amd.com>
---

 arch/arm/dts/versal-mini-emmc0.dts       | 2 +-
 arch/arm/dts/versal-mini-emmc1.dts       | 2 +-
 arch/arm/dts/versal-mini-ospi.dtsi       | 2 +-
 arch/arm/dts/versal-mini-qspi.dtsi       | 2 +-
 arch/arm/dts/versal-mini.dts             | 2 +-
 arch/arm/dts/zynqmp-mini-emmc0.dts       | 2 +-
 arch/arm/dts/zynqmp-mini-emmc1.dts       | 2 +-
 arch/arm/dts/zynqmp-mini-nand.dts        | 2 +-
 arch/arm/dts/zynqmp-mini-qspi.dts        | 2 +-
 arch/arm/dts/zynqmp-zc1254-revA.dts      | 2 +-
 arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 2 +-
 arch/arm/dts/zynqmp-zcu1275-revA.dts     | 2 +-
 arch/arm/dts/zynqmp-zcu1275-revB.dts     | 2 +-
 arch/arm/dts/zynqmp-zcu1285-revA.dts     | 2 +-
 arch/arm/mach-versal/mp.c                | 2 +-
 drivers/fpga/zynqmppl.c                  | 2 +-
 16 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/arm/dts/versal-mini-emmc0.dts b/arch/arm/dts/versal-mini-emmc0.dts
index bd685ddfdb42..60b1c0e1fc44 100644
--- a/arch/arm/dts/versal-mini-emmc0.dts
+++ b/arch/arm/dts/versal-mini-emmc0.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2018-2019, Xilinx, Inc.
  *
- * Siva Durga Prasad <siva.durga.prasad.paladugu at amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu at amd.com>
  * Michal Simek <michal.simek at amd.com>
  */
 
diff --git a/arch/arm/dts/versal-mini-emmc1.dts b/arch/arm/dts/versal-mini-emmc1.dts
index fbdcf5d77f56..751cc38ee5c0 100644
--- a/arch/arm/dts/versal-mini-emmc1.dts
+++ b/arch/arm/dts/versal-mini-emmc1.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2018-2019, Xilinx, Inc.
  *
- * Siva Durga Prasad <siva.durga.prasad.paladugu at amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu at amd.com>
  * Michal Simek <michal.simek at amd.com>
  */
 
diff --git a/arch/arm/dts/versal-mini-ospi.dtsi b/arch/arm/dts/versal-mini-ospi.dtsi
index 5683a2306bde..1abe44f40426 100644
--- a/arch/arm/dts/versal-mini-ospi.dtsi
+++ b/arch/arm/dts/versal-mini-ospi.dtsi
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2018-2019, Xilinx, Inc.
  *
- * Siva Durga Prasad <siva.durga.prasad.paladugu at amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu at amd.com>
  * Michal Simek <michal.simek at amd.com>
  */
 
diff --git a/arch/arm/dts/versal-mini-qspi.dtsi b/arch/arm/dts/versal-mini-qspi.dtsi
index 2fec92ce3ec8..9347ea32c9cb 100644
--- a/arch/arm/dts/versal-mini-qspi.dtsi
+++ b/arch/arm/dts/versal-mini-qspi.dtsi
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2018-2019, Xilinx, Inc.
  *
- * Siva Durga Prasad <siva.durga.prasad.paladugu at amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu at amd.com>
  * Michal Simek <michal.simek at amd.com>
  */
 
diff --git a/arch/arm/dts/versal-mini.dts b/arch/arm/dts/versal-mini.dts
index a213b745bc26..844e3840acec 100644
--- a/arch/arm/dts/versal-mini.dts
+++ b/arch/arm/dts/versal-mini.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2019, Xilinx, Inc.
  *
- * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu at amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu at amd.com>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts
index 08ec2f7b4a9a..02e80bd85e1a 100644
--- a/arch/arm/dts/zynqmp-mini-emmc0.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc0.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2018, Xilinx, Inc.
  *
- * Siva Durga Prasad <siva.durga.prasad.paladugu at amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu at amd.com>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts
index 905de08fdb0b..ce1cdb207538 100644
--- a/arch/arm/dts/zynqmp-mini-emmc1.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc1.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2018, Xilinx, Inc.
  *
- * Siva Durga Prasad <siva.durga.prasad.paladugu at amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu at amd.com>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts
index e5688fd703e6..e0517cf46017 100644
--- a/arch/arm/dts/zynqmp-mini-nand.dts
+++ b/arch/arm/dts/zynqmp-mini-nand.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2018, Xilinx, Inc.
  *
- * Siva Durga Prasad <siva.durga.prasad.paladugu at amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu at amd.com>
  * Michal Simek <michal.simek at amd.com>
  */
 
diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts
index fc0a2e801e49..ee8be5360004 100644
--- a/arch/arm/dts/zynqmp-mini-qspi.dts
+++ b/arch/arm/dts/zynqmp-mini-qspi.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2015 - 2020, Xilinx, Inc.
  *
- * Siva Durga Prasad <siva.durga.prasad.paladugu at amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu at amd.com>
  * Michal Simek <michal.simek at amd.com>
  */
 
diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts
index 5c4acd17cc5d..c6a63201c1c4 100644
--- a/arch/arm/dts/zynqmp-zc1254-revA.dts
+++ b/arch/arm/dts/zynqmp-zc1254-revA.dts
@@ -5,7 +5,7 @@
  * (C) Copyright 2015 - 2020, Xilinx, Inc.
  *
  * Michal Simek <michal.simek at amd.com>
- * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu at amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu at amd.com>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
index 74a5b020e863..0d2ea9c09a0a 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -4,7 +4,7 @@
  *
  * (C) Copyright 2015 - 2021, Xilinx, Inc.
  *
- * Siva Durga Prasad <siva.durga.prasad.paladugu at amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu at amd.com>
  * Michal Simek <michal.simek at amd.com>
  */
 
diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts
index 9404c139a24b..095c972f1322 100644
--- a/arch/arm/dts/zynqmp-zcu1275-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts
@@ -5,7 +5,7 @@
  * (C) Copyright 2017 - 2021, Xilinx, Inc.
  *
  * Michal Simek <michal.simek at amd.com>
- * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu at amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu at amd.com>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts
index c06d262506d0..4060dc3613a2 100644
--- a/arch/arm/dts/zynqmp-zcu1275-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts
@@ -5,7 +5,7 @@
  * (C) Copyright 2018 - 2021, Xilinx, Inc.
  *
  * Michal Simek <michal.simek at amd.com>
- * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu at amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu at amd.com>
  */
 
 /dts-v1/;
diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts
index 99ea143c02ea..4f85837e64f6 100644
--- a/arch/arm/dts/zynqmp-zcu1285-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts
@@ -5,7 +5,7 @@
  * (C) Copyright 2018 - 2021, Xilinx, Inc.
  *
  * Michal Simek <michal.simek at amd.com>
- * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu at amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu at amd.com>
  */
 
 /dts-v1/;
diff --git a/arch/arm/mach-versal/mp.c b/arch/arm/mach-versal/mp.c
index 7bd39289fac5..2487b482ddb1 100644
--- a/arch/arm/mach-versal/mp.c
+++ b/arch/arm/mach-versal/mp.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * (C) Copyright 2019 Xilinx, Inc.
- * Siva Durga Prasad <siva.durga.prasad.paladugu at amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu at amd.com>
  */
 
 #include <common.h>
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index b1f201fb18ba..2656f5fc5ecf 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -2,7 +2,7 @@
 /*
  * (C) Copyright 2015 - 2016, Xilinx, Inc,
  * Michal Simek <michal.simek at amd.com>
- * Siva Durga Prasad <siva.durga.prasad.paladugu at amd.com>>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu at amd.com>
  */
 
 #include <console.h>
-- 
2.36.1



More information about the U-Boot mailing list