[PATCH 03/10] ARM: dts: stm32: add CAN support on stm32f746

[Patrice CHOTARD]

On 9/3/23 22:48, Dario Binacchi wrote:
> commit 0920ccdf41e3078a4dd2567eb905ea154bc826e6 Linux upstream.
> 
> Add support for bxcan (Basic eXtended CAN controller) to STM32F746. The
> chip contains three CAN peripherals, CAN1 and CAN2 in dual peripheral
> configuration and CAN3 in single peripheral configuration:
> - Dual CAN peripheral configuration:
>   * CAN1: Primary bxCAN for managing the communication between a secondary
>     bxCAN and the 512-byte SRAM memory.
>   * CAN2: Secondary bxCAN with no direct access to the SRAM memory.
>   This means that the two bxCAN cells share the 512-byte SRAM memory and
>   CAN2 can't be used without enabling CAN1.
> - Single CAN peripheral configuration:
>   * CAN3: Primary bxCAN with dedicated Memory Access Controller unit and
>     512-byte SRAM memory.
> 
>  -------------------------------------------------------------------------
> | features | CAN1              | CAN2               | CAN 3               |
>  -------------------------------------------------------------------------
> | SRAM     | 512-byte shared between CAN1 & CAN2    | 512-byte            |
>  -------------------------------------------------------------------------
> | Filters  | 26 filters shared between CAN1 & CAN2  | 14 filters          |
>  -------------------------------------------------------------------------
> 
> Signed-off-by: Dario Binacchi <dario.binacchi at amarulasolutions.com>
> Link: https://lore.kernel.org/all/20230427204540.3126234-6-dario.binacchi@amarulasolutions.com
> Signed-off-by: Marc Kleine-Budde <mkl at pengutronix.de>
> ---
> 
>  arch/arm/dts/stm32f746.dtsi | 47 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 47 insertions(+)
> 
> diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
> index c97b3d0d07db..dc5c257fb5fb 100644
> --- a/arch/arm/dts/stm32f746.dtsi
> +++ b/arch/arm/dts/stm32f746.dtsi
> @@ -221,6 +221,23 @@
>  			status = "disabled";
>  		};
>  
> +		can3: can at 40003400 {
> +			compatible = "st,stm32f4-bxcan";
> +			reg = <0x40003400 0x200>;
> +			interrupts = <104>, <105>, <106>, <107>;
> +			interrupt-names = "tx", "rx0", "rx1", "sce";
> +			resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
> +			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
> +			st,gcan = <&gcan3>;
> +			status = "disabled";
> +		};
> +
> +		gcan3: gcan at 40003600 {
> +			compatible = "st,stm32f4-gcan", "syscon";
> +			reg = <0x40003600 0x200>;
> +			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
> +		};
> +
>  		usart2: serial at 40004400 {
>  			compatible = "st,stm32f7-uart";
>  			reg = <0x40004400 0x400>;
> @@ -301,6 +318,36 @@
>  			status = "disabled";
>  		};
>  
> +		can1: can at 40006400 {
> +			compatible = "st,stm32f4-bxcan";
> +			reg = <0x40006400 0x200>;
> +			interrupts = <19>, <20>, <21>, <22>;
> +			interrupt-names = "tx", "rx0", "rx1", "sce";
> +			resets = <&rcc STM32F7_APB1_RESET(CAN1)>;
> +			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
> +			st,can-primary;
> +			st,gcan = <&gcan1>;
> +			status = "disabled";
> +		};
> +
> +		gcan1: gcan at 40006600 {
> +			compatible = "st,stm32f4-gcan", "syscon";
> +			reg = <0x40006600 0x200>;
> +			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
> +		};
> +
> +		can2: can at 40006800 {
> +			compatible = "st,stm32f4-bxcan";
> +			reg = <0x40006800 0x200>;
> +			interrupts = <63>, <64>, <65>, <66>;
> +			interrupt-names = "tx", "rx0", "rx1", "sce";
> +			resets = <&rcc STM32F7_APB1_RESET(CAN2)>;
> +			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>;
> +			st,can-secondary;
> +			st,gcan = <&gcan1>;
> +			status = "disabled";
> +		};
> +
>  		cec: cec at 40006c00 {
>  			compatible = "st,stm32-cec";
>  			reg = <0x40006C00 0x400>;
Reviewed-by: Patrice Chotard <patrice.chotard at foss.st.com>

Thanks
Patrice