[PATCH v2 6/7] phy: rockchip: naneng-combphy: Use signal from comb PHY on RK3588

Kever Yang kever.yang at rock-chips.com
Wed Sep 27 04:47:26 CEST 2023


On 2023/8/3 03:04, Jonas Karlman wrote:
> Route signal from comb PHY instead of PCIe3 PHY to PCIe1l0 and PCIe1l1.
>
> Fixes use of pcie2x1l0 on ROCK 5B.
>
> Code imported from mainline linux driver.
>
> Fixes: c5b4a012bca8 ("phy: rockchip: naneng-combphy: Support rk3588")
> Signed-off-by: Jonas Karlman <jonas at kwiboo.se>
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever
> ---
> v2:
> - New patch
>
>   drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 6 ++++++
>   1 file changed, 6 insertions(+)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> index d5408ccac976..9ca66bf8db92 100644
> --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> @@ -61,6 +61,8 @@ struct rockchip_combphy_grfcfg {
>   	struct combphy_reg pipe_con1_for_sata;
>   	struct combphy_reg pipe_sgmii_mac_sel;
>   	struct combphy_reg pipe_xpcs_phy_ready;
> +	struct combphy_reg pipe_pcie1l0_sel;
> +	struct combphy_reg pipe_pcie1l1_sel;
>   	struct combphy_reg u3otg0_port_en;
>   	struct combphy_reg u3otg1_port_en;
>   };
> @@ -435,6 +437,8 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
>   		param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
>   		param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
>   		param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
> +		param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true);
> +		param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true);
>   		break;
>   	case PHY_TYPE_USB3:
>   		param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
> @@ -507,6 +511,8 @@ static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = {
>   	/* pipe-grf */
>   	.pipe_con0_for_sata	= { 0x0000, 11, 5, 0x00, 0x22 },
>   	.pipe_con1_for_sata	= { 0x0000, 2, 0, 0x00, 0x2 },
> +	.pipe_pcie1l0_sel	= { 0x0100, 0, 0, 0x01, 0x0 },
> +	.pipe_pcie1l1_sel	= { 0x0100, 1, 1, 0x01, 0x0 },
>   };
>   
>   static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {


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