[PATCH] clk: rockchip: rk3399: Add SCLK_UART4_PMU support

[Quentin Schulz]

Hi,

On 4/2/24 12:01, xiaofengvskuye wrote:
> [You don't often get email from xiaofengvskuye at hotmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> 
> The SCLK_UART4_PMU clocks is used as reference clock for UART4 block.
> 
> Add simple support to get rate of SCLK_UART4_PMU clocks to fix
> reference clock period configuration.
> 
> Signed-off-by: xiaofengvskuye <xiaofengvskuye at hotmail.com>
> ---
>   drivers/clk/rockchip/clk_rk3399.c | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index c37e8a53a2..a9114c4b02 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -1563,6 +1563,8 @@ static ulong rk3399_pmuclk_get_rate(struct clk *clk)
>          case SCLK_I2C8_PMU:
>                  rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id);
>                  break;
> +    case SCLK_UART4_PMU:
> +               return 24000000;

Please be mindful about the indentation.

Additionally, UART4 can be at a different rate than 24MHz, it depends on 
the value of uart4_clk_sel (which defaults to 24MHz source clock, indeed).

I would suggest to do this support entirely and handle all three clock 
sources and return the current rate.

Cheers,
Quentin