[PATCH 13/31] clk: rockchip: rk3399: Add dummy support for SCLK_PCIEPHY_REF clock

[Quentin Schulz]

Hi Jonas,

On 3/31/24 22:28, Jonas Karlman wrote:
> rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the
> SCLK_PCIEPHY_REF clock.
> 
> The existing enable/disable ops for SCLK_PCIEPHY_REF already handles
> setting correct parent once the clock gets enabled. And 100 MHz is the
> default rate used for this clock.
> 

I'm not sure that's true?

If I read the TRM correctly, clk_pciephy_ref_sel can come either from 
clk_pcie_ref24m (the default) or clk_pcie_ref100m.

enable/disable is actually only ever writing 0 to that bit (bit 10 in 
CRU_CLKSEL_CON18) and not even enabling the clock.

Assuming clk_pcie_ref24m is the 24MHz base clock (which seems to be the 
case according to the Linux kernel CRU driver), there shouldn't be a way 
to disable that clock. However, if clk_pcie_ref100m is selected, one 
needs to enable/disable it via CRU_CLKGATE_CON12 bit 6 (enabled by default).

set_parent should be properly implemented to handle this parenting and 
enable/disable fixed to use the proper register.

Cheers,
Quentin