[PATCH 13/31] clk: rockchip: rk3399: Add dummy support for SCLK_PCIEPHY_REF clock

[Kever Yang]

On 2024/4/1 04:28, Jonas Karlman wrote:
> rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the
> SCLK_PCIEPHY_REF clock.
>
> The existing enable/disable ops for SCLK_PCIEPHY_REF already handles
> setting correct parent once the clock gets enabled. And 100 MHz is the
> default rate used for this clock.
>
> Add dummy support for setting parent, getting and setting clock rate of
> the SCLK_PCIEPHY_REF clock to allow use of PCIe on affected boards.
>
> Signed-off-by: Jonas Karlman <jonas at kwiboo.se>
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/clk/rockchip/clk_rk3399.c | 4 ++++
>   1 file changed, 4 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index 5934771b4096..29b01abeca06 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -972,6 +972,7 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
>   	case ACLK_GIC_PRE:
>   	case PCLK_DDR:
>   	case ACLK_VDU:
> +	case SCLK_PCIEPHY_REF:
>   		break;
>   	case PCLK_ALIVE:
>   	case PCLK_WDT:
> @@ -1063,6 +1064,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
>   	case ACLK_GIC_PRE:
>   	case PCLK_DDR:
>   	case ACLK_VDU:
> +	case SCLK_PCIEPHY_REF:
>   		return 0;
>   	default:
>   		log_debug("Unknown clock %lu\n", clk->id);
> @@ -1114,6 +1116,8 @@ static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
>   	switch (clk->id) {
>   	case SCLK_RMII_SRC:
>   		return rk3399_gmac_set_parent(clk, parent);
> +	case SCLK_PCIEPHY_REF:
> +		return 0;
>   	}
>   
>   	debug("%s: unsupported clk %ld\n", __func__, clk->id);