[PATCH 5/9] sunxi: H616: DRAM: Adjust configuration procedure
Chris Morgan
macroalpha82 at gmail.com
Fri Aug 2 00:55:15 CEST 2024
From: Jernej Skrabec <jernej.skrabec at gmail.com>
When comparing configuration procedure to vendor driver, I noticed that
one command was out of order and that some delays were missing.
Fix that.
Signed-off-by: Jernej Skrabec <jernej.skrabec at gmail.com>
Tested-by: Chris Morgan <macromorgan at hotmail.com>
---
arch/arm/mach-sunxi/dram_sun50i_h616.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index abb8ee760b..aec561cc94 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -1025,12 +1025,16 @@ static bool mctl_phy_init(const struct dram_para *para,
clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x14c, 0xe0, 0x20);
}
+ clrbits_le32(&mctl_com->unk_0x500, 0x200);
+ udelay(1);
+
clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x14c, 8);
mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x180), 4, 4);
+ udelay(1000);
+
writel(0x37, SUNXI_DRAM_PHY0_BASE + 0x58);
- clrbits_le32(&mctl_com->unk_0x500, 0x200);
writel(0, &mctl_ctl->swctl);
setbits_le32(&mctl_ctl->dfimisc, 1);
@@ -1049,6 +1053,8 @@ static bool mctl_phy_init(const struct dram_para *para,
mctl_await_completion(&mctl_ctl->swstat, 1, 1);
mctl_await_completion(&mctl_ctl->statr, 3, 1);
+ udelay(200);
+
writel(0, &mctl_ctl->swctl);
clrbits_le32(&mctl_ctl->dfimisc, 1);
@@ -1292,8 +1298,10 @@ static bool mctl_ctrl_init(const struct dram_para *para,
setbits_le32(&mctl_ctl->clken, BIT(8));
clrsetbits_le32(&mctl_com->unk_0x500, BIT(24), 0x300);
+ udelay(1);
/* this write seems to enable PHY MMIO region */
setbits_le32(&mctl_com->unk_0x500, BIT(24));
+ udelay(1);
if (!mctl_phy_init(para, config))
return false;
--
2.34.1
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