[PATCH 14/14] clk: mediatek: mt7981: rename CK to CLK
Christian Marangi
ansuelsmth at gmail.com
Fri Aug 2 15:53:15 CEST 2024
Rename each entry from CK to CLK to match the include in upstream kernel
linux.
Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
arch/arm/dts/mt7981.dtsi | 112 ++---
drivers/clk/mediatek/clk-mt7981.c | 552 ++++++++++++-------------
include/dt-bindings/clock/mt7981-clk.h | 382 ++++++++---------
3 files changed, 523 insertions(+), 523 deletions(-)
diff --git a/arch/arm/dts/mt7981.dtsi b/arch/arm/dts/mt7981.dtsi
index 1c54fce7520..a9991a121f1 100644
--- a/arch/arm/dts/mt7981.dtsi
+++ b/arch/arm/dts/mt7981.dtsi
@@ -132,13 +132,13 @@
#clock-cells = <1>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CK_TOP_PWM_SEL>,
- <&infracfg CK_INFRA_PWM_BSEL>,
- <&infracfg CK_INFRA_PWM1_CK>,
- <&infracfg CK_INFRA_PWM2_CK>,
- <&infracfg CK_INFRA_PWM3_CK>;
- assigned-clocks = <&topckgen CK_TOP_PWM_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>;
+ clocks = <&topckgen CLK_TOP_PWM_SEL>,
+ <&infracfg CLK_INFRA_PWM_BSEL>,
+ <&infracfg CLK_INFRA_PWM1_CK>,
+ <&infracfg CLK_INFRA_PWM2_CK>,
+ <&infracfg CLK_INFRA_PWM3_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
status = "disabled";
};
@@ -149,8 +149,8 @@
<0x10217080 0x80>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <1>;
- clocks = <&infracfg CK_INFRA_I2C0_CK>,
- <&infracfg CK_INFRA_AP_DMA_CK>;
+ clocks = <&infracfg CLK_INFRA_I2C0_CK>,
+ <&infracfg CLK_INFRA_AP_DMA_CK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
@@ -161,11 +161,11 @@
compatible = "mediatek,hsuart";
reg = <0x11002000 0x400>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CK_INFRA_UART0_CK>;
- assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg CK_INFRA_UART0_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
- <&topckgen CK_TOP_UART_SEL>;
+ clocks = <&infracfg CLK_INFRA_UART0_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_UART0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
+ <&topckgen CLK_TOP_UART_SEL>;
mediatek,force-highspeed;
status = "disabled";
bootph-all;
@@ -175,11 +175,11 @@
compatible = "mediatek,hsuart";
reg = <0x11003000 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CK_INFRA_UART1_CK>;
- assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg CK_INFRA_UART1_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
- <&topckgen CK_TOP_UART_SEL>;
+ clocks = <&infracfg CLK_INFRA_UART1_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_UART1_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
+ <&topckgen CLK_TOP_UART_SEL>;
mediatek,force-highspeed;
status = "disabled";
};
@@ -188,11 +188,11 @@
compatible = "mediatek,hsuart";
reg = <0x11004000 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CK_INFRA_UART2_CK>;
- assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg CK_INFRA_UART2_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
- <&topckgen CK_TOP_UART_SEL>;
+ clocks = <&infracfg CLK_INFRA_UART2_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_UART2_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
+ <&topckgen CLK_TOP_UART_SEL>;
mediatek,force-highspeed;
status = "disabled";
};
@@ -202,14 +202,14 @@
reg = <0x11005000 0x1000>,
<0x11006000 0x1000>;
reg-names = "nfi", "ecc";
- clocks = <&infracfg CK_INFRA_SPINFI1_CK>,
- <&infracfg CK_INFRA_NFI1_CK>,
- <&infracfg CK_INFRA_NFI_HCK_CK>;
+ clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
+ <&infracfg CLK_INFRA_NFI1_CK>,
+ <&infracfg CLK_INFRA_NFI_HCK_CK>;
clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
- assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
- <&topckgen CK_TOP_NFI1X_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
- <&topckgen CK_TOP_CB_M_D8>;
+ assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
+ <&topckgen CLK_TOP_NFI1X_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
+ <&topckgen CLK_TOP_CB_M_D8>;
status = "disabled";
};
@@ -256,12 +256,12 @@
spi0: spi at 1100a000 {
compatible = "mediatek,ipm-spi";
reg = <0x1100a000 0x100>;
- clocks = <&infracfg CK_INFRA_SPI0_CK>,
- <&topckgen CK_TOP_SPI_SEL>;
- assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
- <&infracfg CK_INFRA_SPI0_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
- <&topckgen CK_TOP_SPI_SEL>;
+ clocks = <&infracfg CLK_INFRA_SPI0_CK>,
+ <&topckgen CLK_TOP_SPI_SEL>;
+ assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>;
clock-names = "spi-clk", "sel-clk";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -271,12 +271,12 @@
compatible = "mediatek,ipm-spi";
reg = <0x1100b000 0x100>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CK_INFRA_SPI1_CK>,
- <&topckgen CK_TOP_SPIM_MST_SEL>;
- assigned-clocks = <&topckgen CK_TOP_SPIM_MST_SEL>,
- <&infracfg CK_INFRA_SPI1_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
- <&topckgen CK_TOP_SPIM_MST_SEL>;
+ clocks = <&infracfg CLK_INFRA_SPI1_CK>,
+ <&topckgen CLK_TOP_SPIM_MST_SEL>;
+ assigned-clocks = <&topckgen CLK_TOP_SPIM_MST_SEL>,
+ <&infracfg CLK_INFRA_SPI1_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
+ <&topckgen CLK_TOP_SPIM_MST_SEL>;
clock-names = "spi-clk", "sel-clk";
status = "disabled";
};
@@ -284,12 +284,12 @@
spi2: spi at 11009000 {
compatible = "mediatek,ipm-spi";
reg = <0x11009000 0x100>;
- clocks = <&infracfg CK_INFRA_SPI2_CK>,
- <&topckgen CK_TOP_SPI_SEL>;
- assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
- <&infracfg CK_INFRA_SPI2_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
- <&topckgen CK_TOP_SPI_SEL>;
+ clocks = <&infracfg CLK_INFRA_SPI2_CK>,
+ <&topckgen CLK_TOP_SPI_SEL>;
+ assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI2_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>;
clock-names = "spi-clk", "sel-clk";
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -300,13 +300,13 @@
reg = <0x11230000 0x1000>,
<0x11C20000 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CK_TOP_EMMC_400M>,
- <&topckgen CK_TOP_EMMC_208M>,
- <&infracfg CK_INFRA_MSDC_CK>;
- assigned-clocks = <&topckgen CK_TOP_EMMC_400M_SEL>,
- <&topckgen CK_TOP_EMMC_208M_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_D2>,
- <&topckgen CK_TOP_CB_M_D2>;
+ clocks = <&topckgen CLK_TOP_EMMC_400M>,
+ <&topckgen CLK_TOP_EMMC_208M>,
+ <&infracfg CLK_INFRA_MSDC_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_EMMC_400M_SEL>,
+ <&topckgen CLK_TOP_EMMC_208M_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D2>,
+ <&topckgen CLK_TOP_CB_M_D2>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};
diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c
index 2c10e36dfec..97073918006 100644
--- a/drivers/clk/mediatek/clk-mt7981.c
+++ b/drivers/clk/mediatek/clk-mt7981.c
@@ -29,204 +29,204 @@
/* FIXED PLLS */
static const struct mtk_fixed_clk fixed_pll_clks[] = {
- FIXED_CLK(CK_APMIXED_ARMPLL, CLK_XTAL, 1300000000),
- FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
- FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 720000000),
- FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
- FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
- FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
- FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000),
- FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000),
+ FIXED_CLK(CLK_APMIXED_ARMPLL, CLK_XTAL, 1300000000),
+ FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
+ FIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 720000000),
+ FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
+ FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
+ FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
+ FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000),
+ FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000),
};
/* TOPCKGEN FIXED CLK */
static const struct mtk_fixed_clk top_fixed_clks[] = {
- FIXED_CLK(CK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000),
+ FIXED_CLK(CLK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000),
};
/* TOPCKGEN FIXED DIV */
static const struct mtk_fixed_factor top_fixed_divs[] = {
- PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_M_D3, "cb_m_d3", CK_APMIXED_MPLL, 1, 3),
- PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4),
- PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8),
- PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16),
- PLL_FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", CK_APMIXED_MMPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_MM_D3, "cb_mm_d3", CK_APMIXED_MMPLL, 1, 3),
- PLL_FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CK_APMIXED_MMPLL, 1, 15),
- PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4),
- PLL_FACTOR(CK_TOP_CB_MM_D6, "cb_mm_d6", CK_APMIXED_MMPLL, 1, 6),
- PLL_FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", CK_APMIXED_MMPLL, 1, 12),
- PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8),
- PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
+ PLL_FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", CLK_APMIXED_MPLL, 1, 1),
+ PLL_FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", CLK_APMIXED_MPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", CLK_APMIXED_MPLL, 1, 3),
+ PLL_FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", CLK_APMIXED_MPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", CLK_APMIXED_MPLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", CLK_APMIXED_MPLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", CLK_APMIXED_MPLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", CLK_APMIXED_MMPLL, 1, 1),
+ PLL_FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", CLK_APMIXED_MMPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", CLK_APMIXED_MMPLL, 1, 3),
+ PLL_FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CLK_APMIXED_MMPLL, 1, 15),
+ PLL_FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", CLK_APMIXED_MMPLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", CLK_APMIXED_MMPLL, 1, 6),
+ PLL_FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", CLK_APMIXED_MMPLL, 1, 12),
+ PLL_FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", CLK_APMIXED_MMPLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", CLK_APMIXED_APLL2, 1,
1),
- PLL_FACTOR(CK_TOP_APLL2_D2, "apll2_d2", CK_APMIXED_APLL2, 1, 2),
- PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4),
- PLL_FACTOR(CK_TOP_NET1_2500M, "net1_2500m", CK_APMIXED_NET1PLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4),
- PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5),
- PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
- PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
- PLL_FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", CK_APMIXED_NET1PLL, 1, 8),
- PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
- PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
- PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1,
+ PLL_FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", CLK_APMIXED_APLL2, 1, 2),
+ PLL_FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", CLK_APMIXED_APLL2, 1, 4),
+ PLL_FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", CLK_APMIXED_NET1PLL, 1, 1),
+ PLL_FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", CLK_APMIXED_NET1PLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", CLK_APMIXED_NET1PLL, 1, 5),
+ PLL_FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", CLK_APMIXED_NET1PLL, 1, 10),
+ PLL_FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", CLK_APMIXED_NET1PLL, 1, 20),
+ PLL_FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", CLK_APMIXED_NET1PLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", CLK_APMIXED_NET1PLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", CLK_APMIXED_NET1PLL, 1, 32),
+ PLL_FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", CLK_APMIXED_NET2PLL, 1,
1),
- PLL_FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", CK_APMIXED_NET2PLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4),
- PLL_FACTOR(CK_TOP_NET2_D4_D2, "net2_d4_d2", CK_APMIXED_NET2PLL, 1, 8),
- PLL_FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", CK_APMIXED_NET2PLL, 1, 16),
- PLL_FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", CK_APMIXED_NET2PLL, 1, 6),
- PLL_FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m",
- CK_APMIXED_WEDMCUPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
- TOP_FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CK_TOP_CB_CKSQ_40M, 1, 2),
- TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1,
+ PLL_FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", CLK_APMIXED_NET2PLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", CLK_APMIXED_NET2PLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", CLK_APMIXED_NET2PLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", CLK_APMIXED_NET2PLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", CLK_APMIXED_NET2PLL, 1, 6),
+ PLL_FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m",
+ CLK_APMIXED_WEDMCUPLL, 1, 1),
+ PLL_FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", CLK_APMIXED_SGMPLL, 1, 1),
+ TOP_FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CLK_TOP_CB_CKSQ_40M, 1, 2),
+ TOP_FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", CLK_TOP_CB_CKSQ_40M, 1,
1250),
- TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1,
+ TOP_FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CLK_TOP_CB_CKSQ_40M, 1,
1220),
- TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_CB_CKSQ_40M, 1, 1),
- TOP_FACTOR(CK_TOP_FAUD, "faud", CK_TOP_AUD_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_CB_CKSQ_40M, 1,
+ TOP_FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", CLK_TOP_CB_CKSQ_40M, 1, 1),
+ TOP_FACTOR(CLK_TOP_FAUD, "faud", CLK_TOP_AUD_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_NFI1X, "nfi1x", CLK_TOP_NFI1X_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CLK_TOP_CB_CKSQ_40M, 1,
1),
- TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_CB_CKSQ_40M, 1, 1),
- TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_CB_CKSQ_40M, 1, 1),
- TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SPI, "spi", CK_TOP_SPI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SPIM_MST, "spim_mst", CK_TOP_SPIM_MST_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_UART_BCK, "uart_bck", CK_TOP_UART_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_PWM_BCK, "pwm_bck", CK_TOP_PWM_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", CK_TOP_PEXTP_TL_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EMMC_208M, "emmc_208m", CK_TOP_EMMC_208M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EMMC_400M, "emmc_400m", CK_TOP_EMMC_400M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_DRAMC_REF, "dramc_ref", CK_TOP_DRAMC_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_DRAMC_MD32, "dramc_md32", CK_TOP_DRAMC_MD32_SEL, 1,
+ TOP_FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", CLK_TOP_CB_CKSQ_40M, 1, 1),
+ TOP_FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", CLK_TOP_CB_CKSQ_40M, 1, 1),
+ TOP_FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", CLK_TOP_SPINFI_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_SPI, "spi", CLK_TOP_SPI_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_SPIM_MST, "spim_mst", CLK_TOP_SPIM_MST_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_UART_BCK, "uart_bck", CLK_TOP_UART_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", CLK_TOP_PWM_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", CLK_TOP_I2C_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", CLK_TOP_PEXTP_TL_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", CLK_TOP_EMMC_208M_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", CLK_TOP_EMMC_400M_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", CLK_TOP_DRAMC_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", CLK_TOP_DRAMC_MD32_SEL, 1,
1),
- TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SYSAPB, "sysapb", CK_TOP_SYSAPB_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_ARM_DB_MAIN, "arm_db_main", CK_TOP_ARM_DB_MAIN_SEL, 1,
+ TOP_FACTOR(CLK_TOP_SYSAXI, "sysaxi", CLK_TOP_SYSAXI_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_SYSAPB, "sysapb", CLK_TOP_SYSAPB_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", CLK_TOP_ARM_DB_MAIN_SEL, 1,
1),
- TOP_FACTOR(CK_TOP_AP2CNN_HOST, "ap2cnn_host", CK_TOP_AP2CNN_HOST_SEL, 1,
+ TOP_FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", CLK_TOP_AP2CNN_HOST_SEL, 1,
1),
- TOP_FACTOR(CK_TOP_NETSYS, "netsys", CK_TOP_NETSYS_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_NETSYS_500M, "netsys_500m", CK_TOP_NETSYS_500M_SEL, 1,
+ TOP_FACTOR(CLK_TOP_NETSYS, "netsys", CLK_TOP_NETSYS_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", CLK_TOP_NETSYS_500M_SEL, 1,
1),
- TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
- CK_TOP_NETSYS_MCU_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SGM_325M, "sgm_325m", CK_TOP_SGM_325M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SGM_REG, "sgm_reg", CK_TOP_SGM_REG_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_F26M, "csw_f26m", CK_TOP_F26M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EIP97B, "eip97b", CK_TOP_EIP97B_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_USB3_PHY, "usb3_phy", CK_TOP_USB3_PHY_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_AUD, "aud", CK_TOP_FAUD, 1, 1),
- TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_U2U3_REF, "u2u3_ref", CK_TOP_U2U3_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_U2U3_SYS, "u2u3_sys", CK_TOP_U2U3_SYS_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_U2U3_XHCI, "u2u3_xhci", CK_TOP_U2U3_XHCI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", CK_TOP_USB_FRMCNT_SEL, 1,
+ TOP_FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
+ CLK_TOP_NETSYS_MCU_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", CLK_TOP_NETSYS_2X_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_SGM_325M, "sgm_325m", CLK_TOP_SGM_325M_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_SGM_REG, "sgm_reg", CLK_TOP_SGM_REG_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_F26M, "csw_f26m", CLK_TOP_F26M_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_EIP97B, "eip97b", CLK_TOP_EIP97B_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", CLK_TOP_USB3_PHY_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_AUD, "aud", CLK_TOP_FAUD, 1, 1),
+ TOP_FACTOR(CLK_TOP_A1SYS, "a1sys", CLK_TOP_A1SYS_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_AUD_L, "aud_l", CLK_TOP_AUD_L_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_A_TUNER, "a_tuner", CLK_TOP_A_TUNER_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", CLK_TOP_U2U3_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", CLK_TOP_U2U3_SYS_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", CLK_TOP_U2U3_XHCI_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", CLK_TOP_USB_FRMCNT_SEL, 1,
1),
};
/* TOPCKGEN MUX PARENTS */
-static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4,
- CK_TOP_NET1_D8_D2, CK_TOP_CB_NET2_D6,
- CK_TOP_CB_M_D4, CK_TOP_CB_MM_D8,
- CK_TOP_NET1_D8_D4, CK_TOP_CB_M_D8 };
+static const int nfi1x_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_MM_D4,
+ CLK_TOP_NET1_D8_D2, CLK_TOP_CB_NET2_D6,
+ CLK_TOP_CB_M_D4, CLK_TOP_CB_MM_D8,
+ CLK_TOP_NET1_D8_D4, CLK_TOP_CB_M_D8 };
-static const int spinfi_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
- CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D4,
- CK_TOP_MM_D6_D2, CK_TOP_CB_M_D8 };
+static const int spinfi_parents[] = { CLK_TOP_CKSQ_40M_D2, CLK_TOP_CB_CKSQ_40M,
+ CLK_TOP_NET1_D5_D4, CLK_TOP_CB_M_D4,
+ CLK_TOP_CB_MM_D8, CLK_TOP_NET1_D8_D4,
+ CLK_TOP_MM_D6_D2, CLK_TOP_CB_M_D8 };
-static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
- CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2,
- CK_TOP_CB_NET2_D6, CK_TOP_NET1_D5_D4,
- CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
+static const int spi_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D2,
+ CLK_TOP_CB_MM_D4, CLK_TOP_NET1_D8_D2,
+ CLK_TOP_CB_NET2_D6, CLK_TOP_NET1_D5_D4,
+ CLK_TOP_CB_M_D4, CLK_TOP_NET1_D8_D4 };
-static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8,
- CK_TOP_M_D8_D2 };
+static const int uart_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D8,
+ CLK_TOP_M_D8_D2 };
-static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
- CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
- CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K };
+static const int pwm_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D8_D2,
+ CLK_TOP_NET1_D5_D4, CLK_TOP_CB_M_D4,
+ CLK_TOP_M_D8_D2, CLK_TOP_CB_RTC_32K };
-static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
- CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
+static const int i2c_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D5_D4,
+ CLK_TOP_CB_M_D4, CLK_TOP_NET1_D8_D4 };
-static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
- CK_TOP_CB_RTC_32K };
+static const int pextp_tl_ck_parents[] = { CLK_TOP_CB_CKSQ_40M,
+ CLK_TOP_NET1_D5_D4, CLK_TOP_CB_M_D4,
+ CLK_TOP_CB_RTC_32K };
static const int emmc_208m_parents[] = {
- CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, CK_TOP_CB_NET2_D4,
- CK_TOP_CB_APLL2_196M, CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2,
- CK_TOP_CB_MM_D6
+ CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D2, CLK_TOP_CB_NET2_D4,
+ CLK_TOP_CB_APLL2_196M, CLK_TOP_CB_MM_D4, CLK_TOP_NET1_D8_D2,
+ CLK_TOP_CB_MM_D6
};
-static const int emmc_400m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D2,
- CK_TOP_CB_MM_D2, CK_TOP_CB_NET2_D2 };
+static const int emmc_400m_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_NET2_D2,
+ CLK_TOP_CB_MM_D2, CLK_TOP_CB_NET2_D2 };
-static const int csw_f26m_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_M_D8_D2 };
+static const int csw_f26m_parents[] = { CLK_TOP_CKSQ_40M_D2, CLK_TOP_M_D8_D2 };
-static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
- CK_TOP_CB_WEDMCU_208M };
+static const int dramc_md32_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D2,
+ CLK_TOP_CB_WEDMCU_208M };
-static const int sysaxi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2 };
+static const int sysaxi_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D8_D2 };
-static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2 };
+static const int sysapb_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_M_D3_D2 };
-static const int arm_db_main_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET2_D6 };
+static const int arm_db_main_parents[] = { CLK_TOP_CB_CKSQ_40M,
+ CLK_TOP_CB_NET2_D6 };
-static const int ap2cnn_host_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET1_D8_D4 };
+static const int ap2cnn_host_parents[] = { CLK_TOP_CB_CKSQ_40M,
+ CLK_TOP_NET1_D8_D4 };
-static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D2 };
+static const int netsys_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_MM_D2 };
-static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET1_D5 };
+static const int netsys_500m_parents[] = { CLK_TOP_CB_CKSQ_40M,
+ CLK_TOP_CB_NET1_D5 };
-static const int netsys_mcu_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_720M,
- CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5,
- CK_TOP_CB_M_416M };
+static const int netsys_mcu_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_MM_720M,
+ CLK_TOP_CB_NET1_D4, CLK_TOP_CB_NET1_D5,
+ CLK_TOP_CB_M_416M };
-static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET2_800M,
- CK_TOP_CB_MM_720M };
+static const int netsys_2x_parents[] = { CLK_TOP_CB_CKSQ_40M,
+ CLK_TOP_CB_NET2_800M,
+ CLK_TOP_CB_MM_720M };
-static const int sgm_325m_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_SGM_325M };
+static const int sgm_325m_parents[] = { CLK_TOP_CB_CKSQ_40M,
+ CLK_TOP_CB_SGM_325M };
-static const int sgm_reg_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D4 };
+static const int sgm_reg_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_NET2_D4 };
-static const int eip97b_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5,
- CK_TOP_CB_M_416M, CK_TOP_CB_MM_D2,
- CK_TOP_NET1_D5_D2 };
+static const int eip97b_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_NET1_D5,
+ CLK_TOP_CB_M_416M, CLK_TOP_CB_MM_D2,
+ CLK_TOP_NET1_D5_D2 };
-static const int aud_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M };
+static const int aud_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_APLL2_196M };
-static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4 };
+static const int a1sys_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_APLL2_D4 };
-static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M,
- CK_TOP_M_D8_D2 };
+static const int aud_l_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_APLL2_196M,
+ CLK_TOP_M_D8_D2 };
-static const int a_tuner_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4,
- CK_TOP_M_D8_D2 };
+static const int a_tuner_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_APLL2_D4,
+ CLK_TOP_M_D8_D2 };
-static const int u2u3_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D8_D2 };
+static const int u2u3_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_M_D8_D2 };
-static const int u2u3_sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 };
+static const int u2u3_sys_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D5_D4 };
-static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_MM_D3_D5 };
+static const int usb_frmcnt_parents[] = { CLK_TOP_CB_CKSQ_40M,
+ CLK_TOP_CB_MM_D3_D5 };
#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
_shift, _width, _gate, _upd_ofs, _upd) \
@@ -242,77 +242,77 @@ static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M,
/* TOPCKGEN MUX_GATE */
static const struct mtk_composite top_muxes[] = {
- TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x0, 0x4, 0x8, 0,
+ TOP_MUX(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x0, 0x4, 0x8, 0,
3, 7, 0x1c0, 0),
- TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x0, 0x4, 0x8,
+ TOP_MUX(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x0, 0x4, 0x8,
8, 3, 15, 0x1c0, 1),
- TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0, 0x4, 0x8, 16, 3,
+ TOP_MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0, 0x4, 0x8, 16, 3,
23, 0x1c0, 2),
- TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x0, 0x4, 0x8,
+ TOP_MUX(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x0, 0x4, 0x8,
24, 3, 31, 0x1c0, 3),
- TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x10, 0x14, 0x18, 0,
+ TOP_MUX(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x10, 0x14, 0x18, 0,
2, 7, 0x1c0, 4),
- TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x10, 0x14, 0x18, 8, 3,
+ TOP_MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x10, 0x14, 0x18, 8, 3,
15, 0x1c0, 5),
- TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x10, 0x14, 0x18, 16, 2,
+ TOP_MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x10, 0x14, 0x18, 16, 2,
23, 0x1c0, 6),
- TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
+ TOP_MUX(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
0x10, 0x14, 0x18, 24, 2, 31, 0x1c0, 7),
- TOP_MUX(CK_TOP_EMMC_208M_SEL, "emmc_208m_sel", emmc_208m_parents, 0x20,
+ TOP_MUX(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel", emmc_208m_parents, 0x20,
0x24, 0x28, 0, 3, 7, 0x1c0, 8),
- TOP_MUX(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20,
+ TOP_MUX(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20,
0x24, 0x28, 8, 2, 15, 0x1c0, 9),
- TOP_MUX(CK_TOP_F26M_SEL, "csw_f26m_sel", csw_f26m_parents, 0x20, 0x24,
+ TOP_MUX(CLK_TOP_F26M_SEL, "csw_f26m_sel", csw_f26m_parents, 0x20, 0x24,
0x28, 16, 1, 23, 0x1c0, 10),
- TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", csw_f26m_parents, 0x20, 0x24,
+ TOP_MUX(CLK_TOP_DRAMC_SEL, "dramc_sel", csw_f26m_parents, 0x20, 0x24,
0x28, 24, 1, 31, 0x1c0, 11),
- TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
+ TOP_MUX(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
0x30, 0x34, 0x38, 0, 2, 7, 0x1c0, 12),
- TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x30, 0x34,
+ TOP_MUX(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x30, 0x34,
0x38, 8, 1, 15, 0x1c0, 13),
- TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x30, 0x34,
+ TOP_MUX(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x30, 0x34,
0x38, 16, 1, 23, 0x1c0, 14),
- TOP_MUX(CK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents,
+ TOP_MUX(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents,
0x30, 0x34, 0x38, 24, 1, 31, 0x1c0, 15),
- TOP_MUX(CK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", ap2cnn_host_parents,
+ TOP_MUX(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", ap2cnn_host_parents,
0x40, 0x44, 0x48, 0, 1, 7, 0x1c0, 16),
- TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x40, 0x44,
+ TOP_MUX(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x40, 0x44,
0x48, 8, 1, 15, 0x1c0, 17),
- TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
+ TOP_MUX(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
0x40, 0x44, 0x48, 16, 1, 23, 0x1c0, 18),
- TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
+ TOP_MUX(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
0x40, 0x44, 0x48, 24, 3, 31, 0x1c0, 19),
- TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x50,
+ TOP_MUX(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x50,
0x54, 0x58, 0, 2, 7, 0x1c0, 20),
- TOP_MUX(CK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x50,
+ TOP_MUX(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x50,
0x54, 0x58, 8, 1, 15, 0x1c0, 21),
- TOP_MUX(CK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x50, 0x54,
+ TOP_MUX(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x50, 0x54,
0x58, 16, 1, 23, 0x1c0, 22),
- TOP_MUX(CK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, 0x50, 0x54,
+ TOP_MUX(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, 0x50, 0x54,
0x58, 24, 3, 31, 0x1c0, 23),
- TOP_MUX(CK_TOP_USB3_PHY_SEL, "usb3_phy_sel", csw_f26m_parents, 0x60,
+ TOP_MUX(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", csw_f26m_parents, 0x60,
0x64, 0x68, 0, 1, 7, 0x1c0, 24),
- TOP_MUX(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x60, 0x64, 0x68, 8, 1,
+ TOP_MUX(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x60, 0x64, 0x68, 8, 1,
15, 0x1c0, 25),
- TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x60, 0x64, 0x68,
+ TOP_MUX(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x60, 0x64, 0x68,
16, 1, 23, 0x1c0, 26),
- TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x60, 0x64, 0x68,
+ TOP_MUX(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x60, 0x64, 0x68,
24, 2, 31, 0x1c0, 27),
- TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x70, 0x74,
+ TOP_MUX(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x70, 0x74,
0x78, 0, 2, 7, 0x1c0, 28),
- TOP_MUX(CK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x70, 0x74, 0x78, 8,
+ TOP_MUX(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x70, 0x74, 0x78, 8,
1, 15, 0x1c0, 29),
- TOP_MUX(CK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x70,
+ TOP_MUX(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x70,
0x74, 0x78, 16, 1, 23, 0x1c0, 30),
- TOP_MUX(CK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x70,
+ TOP_MUX(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x70,
0x74, 0x78, 24, 1, 31, 0x1c4, 0),
- TOP_MUX(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents,
+ TOP_MUX(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents,
0x80, 0x84, 0x88, 0, 1, 7, 0x1c4, 1),
};
/* INFRA FIXED DIV */
static const struct mtk_fixed_factor infra_fixed_divs[] = {
- TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI_SEL, 1, 2),
+ TOP_FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", CLK_TOP_SYSAXI_SEL, 1, 2),
};
/* INFRASYS MUX PARENTS */
@@ -321,37 +321,37 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = {
#define VOID_PARENT PARENT(-1, 0)
static const struct mtk_parent infra_uart0_parents[] = {
- TOP_PARENT(CK_TOP_F26M_SEL),
- TOP_PARENT(CK_TOP_UART_SEL)
+ TOP_PARENT(CLK_TOP_F26M_SEL),
+ TOP_PARENT(CLK_TOP_UART_SEL)
};
static const struct mtk_parent infra_spi0_parents[] = {
- TOP_PARENT(CK_TOP_I2C_SEL),
- TOP_PARENT(CK_TOP_SPI_SEL)
+ TOP_PARENT(CLK_TOP_I2C_SEL),
+ TOP_PARENT(CLK_TOP_SPI_SEL)
};
static const struct mtk_parent infra_spi1_parents[] = {
- TOP_PARENT(CK_TOP_I2C_SEL),
- TOP_PARENT(CK_TOP_SPIM_MST_SEL)
+ TOP_PARENT(CLK_TOP_I2C_SEL),
+ TOP_PARENT(CLK_TOP_SPIM_MST_SEL)
};
static const struct mtk_parent infra_pwm1_parents[] = {
VOID_PARENT,
- TOP_PARENT(CK_TOP_PWM_SEL)
+ TOP_PARENT(CLK_TOP_PWM_SEL)
};
static const struct mtk_parent infra_pwm_bsel_parents[] = {
- TOP_PARENT(CK_TOP_CB_RTC_32P7K),
- TOP_PARENT(CK_TOP_F26M_SEL),
- INFRA_PARENT(CK_INFRA_66M_MCK),
- TOP_PARENT(CK_TOP_PWM_SEL)
+ TOP_PARENT(CLK_TOP_CB_RTC_32P7K),
+ TOP_PARENT(CLK_TOP_F26M_SEL),
+ INFRA_PARENT(CLK_INFRA_66M_MCK),
+ TOP_PARENT(CLK_TOP_PWM_SEL)
};
static const struct mtk_parent infra_pcie_parents[] = {
- TOP_PARENT(CK_TOP_CB_RTC_32P7K),
- TOP_PARENT(CK_TOP_F26M_SEL),
- TOP_PARENT(CK_TOP_CB_CKSQ_40M),
- TOP_PARENT(CK_TOP_PEXTP_TL_SEL)
+ TOP_PARENT(CLK_TOP_CB_RTC_32P7K),
+ TOP_PARENT(CLK_TOP_F26M_SEL),
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ TOP_PARENT(CLK_TOP_PEXTP_TL_SEL)
};
#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \
@@ -365,27 +365,27 @@ static const struct mtk_parent infra_pcie_parents[] = {
/* INFRA MUX */
static const struct mtk_composite infra_muxes[] = {
- INFRA_MUX(CK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents,
+ INFRA_MUX(CLK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents,
0x10, 0, 1),
- INFRA_MUX(CK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents,
+ INFRA_MUX(CLK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents,
0x10, 1, 1),
- INFRA_MUX(CK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents,
+ INFRA_MUX(CLK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents,
0x10, 2, 1),
- INFRA_MUX(CK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10,
+ INFRA_MUX(CLK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10,
4, 1),
- INFRA_MUX(CK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10,
+ INFRA_MUX(CLK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10,
5, 1),
- INFRA_MUX(CK_INFRA_SPI2_SEL, "infra_spi2_sel", infra_spi0_parents, 0x10,
+ INFRA_MUX(CLK_INFRA_SPI2_SEL, "infra_spi2_sel", infra_spi0_parents, 0x10,
6, 1),
- INFRA_MUX(CK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm1_parents, 0x10,
+ INFRA_MUX(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm1_parents, 0x10,
9, 1),
- INFRA_MUX(CK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm1_parents, 0x10,
+ INFRA_MUX(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm1_parents, 0x10,
11, 1),
- INFRA_MUX(CK_INFRA_PWM3_SEL, "infra_pwm3_sel", infra_pwm1_parents, 0x10,
+ INFRA_MUX(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel", infra_pwm1_parents, 0x10,
15, 1),
- INFRA_MUX(CK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents,
+ INFRA_MUX(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents,
0x10, 13, 2),
- INFRA_MUX(CK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20,
+ INFRA_MUX(CLK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20,
0, 2),
};
@@ -442,70 +442,70 @@ static const struct mtk_gate_regs infra_2_cg_regs = {
/* INFRA GATE */
static const struct mtk_gate infracfg_gates[] = {
- GATE_INFRA0_INFRA(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_66M_MCK, 0),
- GATE_INFRA0_INFRA(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_66M_MCK, 1),
- GATE_INFRA0_INFRA(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BSEL, 2),
- GATE_INFRA0_INFRA(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM1_SEL, 3),
- GATE_INFRA0_INFRA(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM2_SEL, 4),
- GATE_INFRA0_INFRA(CK_INFRA_PWM3_CK, "infra_pwm3", CK_INFRA_PWM3_SEL, 27),
- GATE_INFRA0_TOP(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", CK_TOP_SYSAXI, 6),
- GATE_INFRA0_TOP(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", CK_TOP_SYSAXI, 8),
- GATE_INFRA0_TOP(CK_INFRA_AUD_26M_CK, "infra_aud_26m", CK_TOP_F26M_SEL, 9),
- GATE_INFRA0_TOP(CK_INFRA_AUD_L_CK, "infra_aud_l", CK_TOP_AUD_L, 10),
- GATE_INFRA0_TOP(CK_INFRA_AUD_AUD_CK, "infra_aud_aud", CK_TOP_A1SYS,
+ GATE_INFRA0_INFRA(CLK_INFRA_GPT_STA, "infra_gpt_sta", CLK_INFRA_66M_MCK, 0),
+ GATE_INFRA0_INFRA(CLK_INFRA_PWM_HCK, "infra_pwm_hck", CLK_INFRA_66M_MCK, 1),
+ GATE_INFRA0_INFRA(CLK_INFRA_PWM_STA, "infra_pwm_sta", CLK_INFRA_PWM_BSEL, 2),
+ GATE_INFRA0_INFRA(CLK_INFRA_PWM1_CK, "infra_pwm1", CLK_INFRA_PWM1_SEL, 3),
+ GATE_INFRA0_INFRA(CLK_INFRA_PWM2_CK, "infra_pwm2", CLK_INFRA_PWM2_SEL, 4),
+ GATE_INFRA0_INFRA(CLK_INFRA_PWM3_CK, "infra_pwm3", CLK_INFRA_PWM3_SEL, 27),
+ GATE_INFRA0_TOP(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", CLK_TOP_SYSAXI, 6),
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", CLK_TOP_SYSAXI, 8),
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", CLK_TOP_F26M_SEL, 9),
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_L_CK, "infra_aud_l", CLK_TOP_AUD_L, 10),
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", CLK_TOP_A1SYS,
11),
- GATE_INFRA0_TOP(CK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CK_TOP_A_TUNER,
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CLK_TOP_A_TUNER,
13),
- GATE_INFRA0_TOP(CK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CK_TOP_F26M_SEL,
+ GATE_INFRA0_TOP(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CLK_TOP_F26M_SEL,
14),
- GATE_INFRA0_INFRA(CK_INFRA_DBG_CK, "infra_dbg", CK_INFRA_66M_MCK, 15),
- GATE_INFRA0_INFRA(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_66M_MCK, 16),
- GATE_INFRA0_INFRA(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_66M_MCK, 24),
- GATE_INFRA0_TOP(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", CK_TOP_F26M_SEL, 25),
- GATE_INFRA1_TOP(CK_INFRA_THERM_CK, "infra_therm", CK_TOP_F26M_SEL, 0),
- GATE_INFRA1_TOP(CK_INFRA_I2C0_CK, "infra_i2c0", CK_TOP_I2C_BCK, 1),
- GATE_INFRA1_INFRA(CK_INFRA_UART0_CK, "infra_uart0", CK_INFRA_UART0_SEL, 2),
- GATE_INFRA1_INFRA(CK_INFRA_UART1_CK, "infra_uart1", CK_INFRA_UART1_SEL, 3),
- GATE_INFRA1_INFRA(CK_INFRA_UART2_CK, "infra_uart2", CK_INFRA_UART2_SEL, 4),
- GATE_INFRA1_INFRA(CK_INFRA_SPI2_CK, "infra_spi2", CK_INFRA_SPI2_SEL, 6),
- GATE_INFRA1_INFRA(CK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", CK_INFRA_66M_MCK,
+ GATE_INFRA0_INFRA(CLK_INFRA_DBG_CK, "infra_dbg", CLK_INFRA_66M_MCK, 15),
+ GATE_INFRA0_INFRA(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", CLK_INFRA_66M_MCK, 16),
+ GATE_INFRA0_INFRA(CLK_INFRA_SEJ_CK, "infra_sej", CLK_INFRA_66M_MCK, 24),
+ GATE_INFRA0_TOP(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", CLK_TOP_F26M_SEL, 25),
+ GATE_INFRA1_TOP(CLK_INFRA_THERM_CK, "infra_therm", CLK_TOP_F26M_SEL, 0),
+ GATE_INFRA1_TOP(CLK_INFRA_I2C0_CK, "infra_i2c0", CLK_TOP_I2C_BCK, 1),
+ GATE_INFRA1_INFRA(CLK_INFRA_UART0_CK, "infra_uart0", CLK_INFRA_UART0_SEL, 2),
+ GATE_INFRA1_INFRA(CLK_INFRA_UART1_CK, "infra_uart1", CLK_INFRA_UART1_SEL, 3),
+ GATE_INFRA1_INFRA(CLK_INFRA_UART2_CK, "infra_uart2", CLK_INFRA_UART2_SEL, 4),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI2_CK, "infra_spi2", CLK_INFRA_SPI2_SEL, 6),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", CLK_INFRA_66M_MCK,
7),
- GATE_INFRA1_TOP(CK_INFRA_NFI1_CK, "infra_nfi1", CK_TOP_NFI1X, 8),
- GATE_INFRA1_TOP(CK_INFRA_SPINFI1_CK, "infra_spinfi1", CK_TOP_SPINFI_BCK,
- 9),
- GATE_INFRA1_INFRA(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CK_INFRA_66M_MCK, 10),
- GATE_INFRA1_INFRA(CK_INFRA_SPI0_CK, "infra_spi0", CK_INFRA_SPI0_SEL, 11),
- GATE_INFRA1_INFRA(CK_INFRA_SPI1_CK, "infra_spi1", CK_INFRA_SPI1_SEL, 12),
- GATE_INFRA1_INFRA(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CK_INFRA_66M_MCK,
+ GATE_INFRA1_TOP(CLK_INFRA_NFI1_CK, "infra_nfi1", CLK_TOP_NFI1X, 8),
+ GATE_INFRA1_TOP(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", CLK_TOP_SPINFI_BCK,
+ 9),
+ GATE_INFRA1_INFRA(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CLK_INFRA_66M_MCK, 10),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI0_CK, "infra_spi0", CLK_INFRA_SPI0_SEL, 11),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI1_CK, "infra_spi1", CLK_INFRA_SPI1_SEL, 12),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CLK_INFRA_66M_MCK,
13),
- GATE_INFRA1_INFRA(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CK_INFRA_66M_MCK,
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CLK_INFRA_66M_MCK,
14),
- GATE_INFRA1_TOP(CK_INFRA_FRTC_CK, "infra_frtc", CK_TOP_CB_RTC_32K, 15),
- GATE_INFRA1_TOP(CK_INFRA_MSDC_CK, "infra_msdc", CK_TOP_EMMC_400M, 16),
- GATE_INFRA1_TOP(CK_INFRA_MSDC_HCK_CK, "infra_msdc_hck",
- CK_TOP_EMMC_208M, 17),
- GATE_INFRA1_TOP(CK_INFRA_MSDC_133M_CK, "infra_msdc_133m",
- CK_TOP_SYSAXI, 18),
- GATE_INFRA1_TOP(CK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CK_TOP_SYSAXI,
+ GATE_INFRA1_TOP(CLK_INFRA_FRTC_CK, "infra_frtc", CLK_TOP_CB_RTC_32K, 15),
+ GATE_INFRA1_TOP(CLK_INFRA_MSDC_CK, "infra_msdc", CLK_TOP_EMMC_400M, 16),
+ GATE_INFRA1_TOP(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck",
+ CLK_TOP_EMMC_208M, 17),
+ GATE_INFRA1_TOP(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m",
+ CLK_TOP_SYSAXI, 18),
+ GATE_INFRA1_TOP(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CLK_TOP_SYSAXI,
19),
- GATE_INFRA1_INFRA(CK_INFRA_ADC_26M_CK, "infra_adc_26m", CK_INFRA_ADC_FRC_CK, 20),
- GATE_INFRA1_TOP(CK_INFRA_ADC_FRC_CK, "infra_adc_frc", CK_TOP_F26M, 21),
- GATE_INFRA1_TOP(CK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CK_TOP_NFI1X,
+ GATE_INFRA1_INFRA(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", CLK_INFRA_ADC_FRC_CK, 20),
+ GATE_INFRA1_TOP(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", CLK_TOP_F26M, 21),
+ GATE_INFRA1_TOP(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CLK_TOP_NFI1X,
23),
- GATE_INFRA1_TOP(CK_INFRA_I2C_MCK_CK, "infra_i2c_mck", CK_TOP_SYSAXI,
+ GATE_INFRA1_TOP(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", CLK_TOP_SYSAXI,
25),
- GATE_INFRA1_INFRA(CK_INFRA_I2C_PCK_CK, "infra_i2c_pck", CK_INFRA_66M_MCK, 26),
- GATE_INFRA2_TOP(CK_INFRA_IUSB_133_CK, "infra_iusb_133", CK_TOP_SYSAXI,
+ GATE_INFRA1_INFRA(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", CLK_INFRA_66M_MCK, 26),
+ GATE_INFRA2_TOP(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", CLK_TOP_SYSAXI,
0),
- GATE_INFRA2_TOP(CK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CK_TOP_SYSAXI,
+ GATE_INFRA2_TOP(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CLK_TOP_SYSAXI,
1),
- GATE_INFRA2_TOP(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CK_TOP_U2U3_SYS,
+ GATE_INFRA2_TOP(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CLK_TOP_U2U3_SYS,
2),
- GATE_INFRA2_TOP(CK_INFRA_IUSB_CK, "infra_iusb", CK_TOP_U2U3_REF, 3),
- GATE_INFRA2_TOP(CK_INFRA_IPCIE_CK, "infra_ipcie", CK_TOP_PEXTP_TL, 12),
- GATE_INFRA2_TOP(CK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", CK_TOP_CB_CKSQ_40M, 13),
- GATE_INFRA2_TOP(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_TOP_F26M, 14),
- GATE_INFRA2_TOP(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_TOP_SYSAXI, 15),
+ GATE_INFRA2_TOP(CLK_INFRA_IUSB_CK, "infra_iusb", CLK_TOP_U2U3_REF, 3),
+ GATE_INFRA2_TOP(CLK_INFRA_IPCIE_CK, "infra_ipcie", CLK_TOP_PEXTP_TL, 12),
+ GATE_INFRA2_TOP(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", CLK_TOP_CB_CKSQ_40M, 13),
+ GATE_INFRA2_TOP(CLK_INFRA_IPCIER_CK, "infra_ipcier", CLK_TOP_F26M, 14),
+ GATE_INFRA2_TOP(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", CLK_TOP_SYSAXI, 15),
};
static const struct mtk_clk_tree mt7981_fixed_pll_clk_tree = {
@@ -515,8 +515,8 @@ static const struct mtk_clk_tree mt7981_fixed_pll_clk_tree = {
};
static const struct mtk_clk_tree mt7981_topckgen_clk_tree = {
- .fdivs_offs = CK_TOP_CB_M_416M,
- .muxes_offs = CK_TOP_NFI1X_SEL,
+ .fdivs_offs = CLK_TOP_CB_M_416M,
+ .muxes_offs = CLK_TOP_NFI1X_SEL,
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
@@ -524,9 +524,9 @@ static const struct mtk_clk_tree mt7981_topckgen_clk_tree = {
};
static const struct mtk_clk_tree mt7981_infracfg_clk_tree = {
- .fdivs_offs = CK_INFRA_66M_MCK,
- .muxes_offs = CK_INFRA_UART0_SEL,
- .gates_offs = CK_INFRA_GPT_STA,
+ .fdivs_offs = CLK_INFRA_66M_MCK,
+ .muxes_offs = CLK_INFRA_UART0_SEL,
+ .gates_offs = CLK_INFRA_GPT_STA,
.fdivs = infra_fixed_divs,
.muxes = infra_muxes,
.gates = infracfg_gates,
@@ -614,10 +614,10 @@ static const struct mtk_gate_regs sgmii_cg_regs = {
}
static const struct mtk_gate sgmii0_cgs[] = {
- GATE_SGMII(CK_SGM0_TX_EN, "sgm0_tx_en", CK_TOP_USB_TX250M, 2),
- GATE_SGMII(CK_SGM0_RX_EN, "sgm0_rx_en", CK_TOP_USB_EQ_RX250M, 3),
- GATE_SGMII(CK_SGM0_CK0_EN, "sgm0_ck0_en", CK_TOP_USB_LN0_CK, 4),
- GATE_SGMII(CK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", CK_TOP_USB_CDR_CK, 5),
+ GATE_SGMII(CLK_SGM0_TX_EN, "sgm0_tx_en", CLK_TOP_USB_TX250M, 2),
+ GATE_SGMII(CLK_SGM0_RX_EN, "sgm0_rx_en", CLK_TOP_USB_EQ_RX250M, 3),
+ GATE_SGMII(CLK_SGM0_CK0_EN, "sgm0_ck0_en", CLK_TOP_USB_LN0_CK, 4),
+ GATE_SGMII(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", CLK_TOP_USB_CDR_CK, 5),
};
static int mt7981_sgmii0sys_probe(struct udevice *dev)
@@ -641,10 +641,10 @@ U_BOOT_DRIVER(mtk_clk_sgmii0sys) = {
};
static const struct mtk_gate sgmii1_cgs[] = {
- GATE_SGMII(CK_SGM1_TX_EN, "sgm1_tx_en", CK_TOP_USB_TX250M, 2),
- GATE_SGMII(CK_SGM1_RX_EN, "sgm1_rx_en", CK_TOP_USB_EQ_RX250M, 3),
- GATE_SGMII(CK_SGM1_CK1_EN, "sgm1_ck1_en", CK_TOP_USB_LN0_CK, 4),
- GATE_SGMII(CK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", CK_TOP_USB_CDR_CK, 5),
+ GATE_SGMII(CLK_SGM1_TX_EN, "sgm1_tx_en", CLK_TOP_USB_TX250M, 2),
+ GATE_SGMII(CLK_SGM1_RX_EN, "sgm1_rx_en", CLK_TOP_USB_EQ_RX250M, 3),
+ GATE_SGMII(CLK_SGM1_CK1_EN, "sgm1_ck1_en", CLK_TOP_USB_LN0_CK, 4),
+ GATE_SGMII(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", CLK_TOP_USB_CDR_CK, 5),
};
static int mt7981_sgmii1sys_probe(struct udevice *dev)
@@ -682,10 +682,10 @@ static const struct mtk_gate_regs eth_cg_regs = {
}
static const struct mtk_gate eth_cgs[] = {
- GATE_ETH(CK_ETH_FE_EN, "eth_fe_en", CK_TOP_NETSYS_2X, 6),
- GATE_ETH(CK_ETH_GP2_EN, "eth_gp2_en", CK_TOP_SGM_325M, 7),
- GATE_ETH(CK_ETH_GP1_EN, "eth_gp1_en", CK_TOP_SGM_325M, 8),
- GATE_ETH(CK_ETH_WOCPU0_EN, "eth_wocpu0_en", CK_TOP_NETSYS_WED_MCU, 15),
+ GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", CLK_TOP_NETSYS_2X, 6),
+ GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", CLK_TOP_SGM_325M, 7),
+ GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", CLK_TOP_SGM_325M, 8),
+ GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", CLK_TOP_NETSYS_WED_MCU, 15),
};
static int mt7981_ethsys_probe(struct udevice *dev)
diff --git a/include/dt-bindings/clock/mt7981-clk.h b/include/dt-bindings/clock/mt7981-clk.h
index 05019c95ebe..52325916015 100644
--- a/include/dt-bindings/clock/mt7981-clk.h
+++ b/include/dt-bindings/clock/mt7981-clk.h
@@ -10,217 +10,217 @@
/* TOPCKGEN */
-#define CK_TOP_CB_CKSQ_40M 0
-#define CK_TOP_CB_M_416M 1
-#define CK_TOP_CB_M_D2 2
-#define CK_TOP_CB_M_D3 3
-#define CK_TOP_M_D3_D2 4
-#define CK_TOP_CB_M_D4 5
-#define CK_TOP_CB_M_D8 6
-#define CK_TOP_M_D8_D2 7
-#define CK_TOP_CB_MM_720M 8
-#define CK_TOP_CB_MM_D2 9
-#define CK_TOP_CB_MM_D3 10
-#define CK_TOP_CB_MM_D3_D5 11
-#define CK_TOP_CB_MM_D4 12
-#define CK_TOP_CB_MM_D6 13
-#define CK_TOP_MM_D6_D2 14
-#define CK_TOP_CB_MM_D8 15
-#define CK_TOP_CB_APLL2_196M 16
-#define CK_TOP_APLL2_D2 17
-#define CK_TOP_APLL2_D4 18
-#define CK_TOP_NET1_2500M 19
-#define CK_TOP_CB_NET1_D4 20
-#define CK_TOP_CB_NET1_D5 21
-#define CK_TOP_NET1_D5_D2 22
-#define CK_TOP_NET1_D5_D4 23
-#define CK_TOP_CB_NET1_D8 24
-#define CK_TOP_NET1_D8_D2 25
-#define CK_TOP_NET1_D8_D4 26
-#define CK_TOP_CB_NET2_800M 27
-#define CK_TOP_CB_NET2_D2 28
-#define CK_TOP_CB_NET2_D4 29
-#define CK_TOP_NET2_D4_D2 30
-#define CK_TOP_NET2_D4_D4 31
-#define CK_TOP_CB_NET2_D6 32
-#define CK_TOP_CB_WEDMCU_208M 33
-#define CK_TOP_CB_SGM_325M 34
-#define CK_TOP_CKSQ_40M_D2 35
-#define CK_TOP_CB_RTC_32K 36
-#define CK_TOP_CB_RTC_32P7K 37
-#define CK_TOP_USB_TX250M 38
-#define CK_TOP_FAUD 39
-#define CK_TOP_NFI1X 40
-#define CK_TOP_USB_EQ_RX250M 41
-#define CK_TOP_USB_CDR_CK 42
-#define CK_TOP_USB_LN0_CK 43
-#define CK_TOP_SPINFI_BCK 44
-#define CK_TOP_SPI 45
-#define CK_TOP_SPIM_MST 46
-#define CK_TOP_UART_BCK 47
-#define CK_TOP_PWM_BCK 48
-#define CK_TOP_I2C_BCK 49
-#define CK_TOP_PEXTP_TL 50
-#define CK_TOP_EMMC_208M 51
-#define CK_TOP_EMMC_400M 52
-#define CK_TOP_DRAMC_REF 53
-#define CK_TOP_DRAMC_MD32 54
-#define CK_TOP_SYSAXI 55
-#define CK_TOP_SYSAPB 56
-#define CK_TOP_ARM_DB_MAIN 57
-#define CK_TOP_AP2CNN_HOST 58
-#define CK_TOP_NETSYS 59
-#define CK_TOP_NETSYS_500M 60
-#define CK_TOP_NETSYS_WED_MCU 61
-#define CK_TOP_NETSYS_2X 62
-#define CK_TOP_SGM_325M 63
-#define CK_TOP_SGM_REG 64
-#define CK_TOP_F26M 65
-#define CK_TOP_EIP97B 66
-#define CK_TOP_USB3_PHY 67
-#define CK_TOP_AUD 68
-#define CK_TOP_A1SYS 69
-#define CK_TOP_AUD_L 70
-#define CK_TOP_A_TUNER 71
-#define CK_TOP_U2U3_REF 72
-#define CK_TOP_U2U3_SYS 73
-#define CK_TOP_U2U3_XHCI 74
-#define CK_TOP_USB_FRMCNT 75
-#define CK_TOP_NFI1X_SEL 76
-#define CK_TOP_SPINFI_SEL 77
-#define CK_TOP_SPI_SEL 78
-#define CK_TOP_SPIM_MST_SEL 79
-#define CK_TOP_UART_SEL 80
-#define CK_TOP_PWM_SEL 81
-#define CK_TOP_I2C_SEL 82
-#define CK_TOP_PEXTP_TL_SEL 83
-#define CK_TOP_EMMC_208M_SEL 84
-#define CK_TOP_EMMC_400M_SEL 85
-#define CK_TOP_F26M_SEL 86
-#define CK_TOP_DRAMC_SEL 87
-#define CK_TOP_DRAMC_MD32_SEL 88
-#define CK_TOP_SYSAXI_SEL 89
-#define CK_TOP_SYSAPB_SEL 90
-#define CK_TOP_ARM_DB_MAIN_SEL 91
-#define CK_TOP_AP2CNN_HOST_SEL 92
-#define CK_TOP_NETSYS_SEL 93
-#define CK_TOP_NETSYS_500M_SEL 94
-#define CK_TOP_NETSYS_MCU_SEL 95
-#define CK_TOP_NETSYS_2X_SEL 96
-#define CK_TOP_SGM_325M_SEL 97
-#define CK_TOP_SGM_REG_SEL 98
-#define CK_TOP_EIP97B_SEL 99
-#define CK_TOP_USB3_PHY_SEL 100
-#define CK_TOP_AUD_SEL 101
-#define CK_TOP_A1SYS_SEL 102
-#define CK_TOP_AUD_L_SEL 103
-#define CK_TOP_A_TUNER_SEL 104
-#define CK_TOP_U2U3_SEL 105
-#define CK_TOP_U2U3_SYS_SEL 106
-#define CK_TOP_U2U3_XHCI_SEL 107
-#define CK_TOP_USB_FRMCNT_SEL 108
-#define CK_TOP_AUD_I2S_M 109
+#define CLK_TOP_CB_CKSQ_40M 0
+#define CLK_TOP_CB_M_416M 1
+#define CLK_TOP_CB_M_D2 2
+#define CLK_TOP_CB_M_D3 3
+#define CLK_TOP_M_D3_D2 4
+#define CLK_TOP_CB_M_D4 5
+#define CLK_TOP_CB_M_D8 6
+#define CLK_TOP_M_D8_D2 7
+#define CLK_TOP_CB_MM_720M 8
+#define CLK_TOP_CB_MM_D2 9
+#define CLK_TOP_CB_MM_D3 10
+#define CLK_TOP_CB_MM_D3_D5 11
+#define CLK_TOP_CB_MM_D4 12
+#define CLK_TOP_CB_MM_D6 13
+#define CLK_TOP_MM_D6_D2 14
+#define CLK_TOP_CB_MM_D8 15
+#define CLK_TOP_CB_APLL2_196M 16
+#define CLK_TOP_APLL2_D2 17
+#define CLK_TOP_APLL2_D4 18
+#define CLK_TOP_NET1_2500M 19
+#define CLK_TOP_CB_NET1_D4 20
+#define CLK_TOP_CB_NET1_D5 21
+#define CLK_TOP_NET1_D5_D2 22
+#define CLK_TOP_NET1_D5_D4 23
+#define CLK_TOP_CB_NET1_D8 24
+#define CLK_TOP_NET1_D8_D2 25
+#define CLK_TOP_NET1_D8_D4 26
+#define CLK_TOP_CB_NET2_800M 27
+#define CLK_TOP_CB_NET2_D2 28
+#define CLK_TOP_CB_NET2_D4 29
+#define CLK_TOP_NET2_D4_D2 30
+#define CLK_TOP_NET2_D4_D4 31
+#define CLK_TOP_CB_NET2_D6 32
+#define CLK_TOP_CB_WEDMCU_208M 33
+#define CLK_TOP_CB_SGM_325M 34
+#define CLK_TOP_CKSQ_40M_D2 35
+#define CLK_TOP_CB_RTC_32K 36
+#define CLK_TOP_CB_RTC_32P7K 37
+#define CLK_TOP_USB_TX250M 38
+#define CLK_TOP_FAUD 39
+#define CLK_TOP_NFI1X 40
+#define CLK_TOP_USB_EQ_RX250M 41
+#define CLK_TOP_USB_CDR_CK 42
+#define CLK_TOP_USB_LN0_CK 43
+#define CLK_TOP_SPINFI_BCK 44
+#define CLK_TOP_SPI 45
+#define CLK_TOP_SPIM_MST 46
+#define CLK_TOP_UART_BCK 47
+#define CLK_TOP_PWM_BCK 48
+#define CLK_TOP_I2C_BCK 49
+#define CLK_TOP_PEXTP_TL 50
+#define CLK_TOP_EMMC_208M 51
+#define CLK_TOP_EMMC_400M 52
+#define CLK_TOP_DRAMC_REF 53
+#define CLK_TOP_DRAMC_MD32 54
+#define CLK_TOP_SYSAXI 55
+#define CLK_TOP_SYSAPB 56
+#define CLK_TOP_ARM_DB_MAIN 57
+#define CLK_TOP_AP2CNN_HOST 58
+#define CLK_TOP_NETSYS 59
+#define CLK_TOP_NETSYS_500M 60
+#define CLK_TOP_NETSYS_WED_MCU 61
+#define CLK_TOP_NETSYS_2X 62
+#define CLK_TOP_SGM_325M 63
+#define CLK_TOP_SGM_REG 64
+#define CLK_TOP_F26M 65
+#define CLK_TOP_EIP97B 66
+#define CLK_TOP_USB3_PHY 67
+#define CLK_TOP_AUD 68
+#define CLK_TOP_A1SYS 69
+#define CLK_TOP_AUD_L 70
+#define CLK_TOP_A_TUNER 71
+#define CLK_TOP_U2U3_REF 72
+#define CLK_TOP_U2U3_SYS 73
+#define CLK_TOP_U2U3_XHCI 74
+#define CLK_TOP_USB_FRMCNT 75
+#define CLK_TOP_NFI1X_SEL 76
+#define CLK_TOP_SPINFI_SEL 77
+#define CLK_TOP_SPI_SEL 78
+#define CLK_TOP_SPIM_MST_SEL 79
+#define CLK_TOP_UART_SEL 80
+#define CLK_TOP_PWM_SEL 81
+#define CLK_TOP_I2C_SEL 82
+#define CLK_TOP_PEXTP_TL_SEL 83
+#define CLK_TOP_EMMC_208M_SEL 84
+#define CLK_TOP_EMMC_400M_SEL 85
+#define CLK_TOP_F26M_SEL 86
+#define CLK_TOP_DRAMC_SEL 87
+#define CLK_TOP_DRAMC_MD32_SEL 88
+#define CLK_TOP_SYSAXI_SEL 89
+#define CLK_TOP_SYSAPB_SEL 90
+#define CLK_TOP_ARM_DB_MAIN_SEL 91
+#define CLK_TOP_AP2CNN_HOST_SEL 92
+#define CLK_TOP_NETSYS_SEL 93
+#define CLK_TOP_NETSYS_500M_SEL 94
+#define CLK_TOP_NETSYS_MCU_SEL 95
+#define CLK_TOP_NETSYS_2X_SEL 96
+#define CLK_TOP_SGM_325M_SEL 97
+#define CLK_TOP_SGM_REG_SEL 98
+#define CLK_TOP_EIP97B_SEL 99
+#define CLK_TOP_USB3_PHY_SEL 100
+#define CLK_TOP_AUD_SEL 101
+#define CLK_TOP_A1SYS_SEL 102
+#define CLK_TOP_AUD_L_SEL 103
+#define CLK_TOP_A_TUNER_SEL 104
+#define CLK_TOP_U2U3_SEL 105
+#define CLK_TOP_U2U3_SYS_SEL 106
+#define CLK_TOP_U2U3_XHCI_SEL 107
+#define CLK_TOP_USB_FRMCNT_SEL 108
+#define CLK_TOP_AUD_I2S_M 109
#define CLK_TOP_NR_CLK 110
/* INFRACFG */
-#define CK_INFRA_66M_MCK 0
-#define CK_INFRA_UART0_SEL 1
-#define CK_INFRA_UART1_SEL 2
-#define CK_INFRA_UART2_SEL 3
-#define CK_INFRA_SPI0_SEL 4
-#define CK_INFRA_SPI1_SEL 5
-#define CK_INFRA_SPI2_SEL 6
-#define CK_INFRA_PWM1_SEL 7
-#define CK_INFRA_PWM2_SEL 8
-#define CK_INFRA_PWM3_SEL 9
-#define CK_INFRA_PWM_BSEL 10
-#define CK_INFRA_PCIE_SEL 11
-#define CK_INFRA_GPT_STA 12
-#define CK_INFRA_PWM_HCK 13
-#define CK_INFRA_PWM_STA 14
-#define CK_INFRA_PWM1_CK 15
-#define CK_INFRA_PWM2_CK 16
-#define CK_INFRA_PWM3_CK 17
-#define CK_INFRA_CQ_DMA_CK 18
-#define CK_INFRA_AUD_BUS_CK 19
-#define CK_INFRA_AUD_26M_CK 20
-#define CK_INFRA_AUD_L_CK 21
-#define CK_INFRA_AUD_AUD_CK 22
-#define CK_INFRA_AUD_EG2_CK 23
-#define CK_INFRA_DRAMC_26M_CK 24
-#define CK_INFRA_DBG_CK 25
-#define CK_INFRA_AP_DMA_CK 26
-#define CK_INFRA_SEJ_CK 27
-#define CK_INFRA_SEJ_13M_CK 28
-#define CK_INFRA_THERM_CK 29
-#define CK_INFRA_I2C0_CK 30
-#define CK_INFRA_UART0_CK 31
-#define CK_INFRA_UART1_CK 32
-#define CK_INFRA_UART2_CK 33
-#define CK_INFRA_SPI2_CK 34
-#define CK_INFRA_SPI2_HCK_CK 35
-#define CK_INFRA_NFI1_CK 36
-#define CK_INFRA_SPINFI1_CK 37
-#define CK_INFRA_NFI_HCK_CK 38
-#define CK_INFRA_SPI0_CK 39
-#define CK_INFRA_SPI1_CK 40
-#define CK_INFRA_SPI0_HCK_CK 41
-#define CK_INFRA_SPI1_HCK_CK 42
-#define CK_INFRA_FRTC_CK 43
-#define CK_INFRA_MSDC_CK 44
-#define CK_INFRA_MSDC_HCK_CK 45
-#define CK_INFRA_MSDC_133M_CK 46
-#define CK_INFRA_MSDC_66M_CK 47
-#define CK_INFRA_ADC_26M_CK 48
-#define CK_INFRA_ADC_FRC_CK 49
-#define CK_INFRA_FBIST2FPC_CK 50
-#define CK_INFRA_I2C_MCK_CK 51
-#define CK_INFRA_I2C_PCK_CK 52
-#define CK_INFRA_IUSB_133_CK 53
-#define CK_INFRA_IUSB_66M_CK 54
-#define CK_INFRA_IUSB_SYS_CK 55
-#define CK_INFRA_IUSB_CK 56
-#define CK_INFRA_IPCIE_CK 57
-#define CK_INFRA_IPCIE_PIPE_CK 58
-#define CK_INFRA_IPCIER_CK 59
-#define CK_INFRA_IPCIEB_CK 60
+#define CLK_INFRA_66M_MCK 0
+#define CLK_INFRA_UART0_SEL 1
+#define CLK_INFRA_UART1_SEL 2
+#define CLK_INFRA_UART2_SEL 3
+#define CLK_INFRA_SPI0_SEL 4
+#define CLK_INFRA_SPI1_SEL 5
+#define CLK_INFRA_SPI2_SEL 6
+#define CLK_INFRA_PWM1_SEL 7
+#define CLK_INFRA_PWM2_SEL 8
+#define CLK_INFRA_PWM3_SEL 9
+#define CLK_INFRA_PWM_BSEL 10
+#define CLK_INFRA_PCIE_SEL 11
+#define CLK_INFRA_GPT_STA 12
+#define CLK_INFRA_PWM_HCK 13
+#define CLK_INFRA_PWM_STA 14
+#define CLK_INFRA_PWM1_CK 15
+#define CLK_INFRA_PWM2_CK 16
+#define CLK_INFRA_PWM3_CK 17
+#define CLK_INFRA_CQ_DMA_CK 18
+#define CLK_INFRA_AUD_BUS_CK 19
+#define CLK_INFRA_AUD_26M_CK 20
+#define CLK_INFRA_AUD_L_CK 21
+#define CLK_INFRA_AUD_AUD_CK 22
+#define CLK_INFRA_AUD_EG2_CK 23
+#define CLK_INFRA_DRAMC_26M_CK 24
+#define CLK_INFRA_DBG_CK 25
+#define CLK_INFRA_AP_DMA_CK 26
+#define CLK_INFRA_SEJ_CK 27
+#define CLK_INFRA_SEJ_13M_CK 28
+#define CLK_INFRA_THERM_CK 29
+#define CLK_INFRA_I2C0_CK 30
+#define CLK_INFRA_UART0_CK 31
+#define CLK_INFRA_UART1_CK 32
+#define CLK_INFRA_UART2_CK 33
+#define CLK_INFRA_SPI2_CK 34
+#define CLK_INFRA_SPI2_HCK_CK 35
+#define CLK_INFRA_NFI1_CK 36
+#define CLK_INFRA_SPINFI1_CK 37
+#define CLK_INFRA_NFI_HCK_CK 38
+#define CLK_INFRA_SPI0_CK 39
+#define CLK_INFRA_SPI1_CK 40
+#define CLK_INFRA_SPI0_HCK_CK 41
+#define CLK_INFRA_SPI1_HCK_CK 42
+#define CLK_INFRA_FRTC_CK 43
+#define CLK_INFRA_MSDC_CK 44
+#define CLK_INFRA_MSDC_HCK_CK 45
+#define CLK_INFRA_MSDC_133M_CK 46
+#define CLK_INFRA_MSDC_66M_CK 47
+#define CLK_INFRA_ADC_26M_CK 48
+#define CLK_INFRA_ADC_FRC_CK 49
+#define CLK_INFRA_FBIST2FPC_CK 50
+#define CLK_INFRA_I2C_MCK_CK 51
+#define CLK_INFRA_I2C_PCK_CK 52
+#define CLK_INFRA_IUSB_133_CK 53
+#define CLK_INFRA_IUSB_66M_CK 54
+#define CLK_INFRA_IUSB_SYS_CK 55
+#define CLK_INFRA_IUSB_CK 56
+#define CLK_INFRA_IPCIE_CK 57
+#define CLK_INFRA_IPCIE_PIPE_CK 58
+#define CLK_INFRA_IPCIER_CK 59
+#define CLK_INFRA_IPCIEB_CK 60
#define CLK_INFRA_NR_CLK 61
/* APMIXEDSYS */
-#define CK_APMIXED_ARMPLL 0
-#define CK_APMIXED_NET2PLL 1
-#define CK_APMIXED_MMPLL 2
-#define CK_APMIXED_SGMPLL 3
-#define CK_APMIXED_WEDMCUPLL 4
-#define CK_APMIXED_NET1PLL 5
-#define CK_APMIXED_MPLL 6
-#define CK_APMIXED_APLL2 7
+#define CLK_APMIXED_ARMPLL 0
+#define CLK_APMIXED_NET2PLL 1
+#define CLK_APMIXED_MMPLL 2
+#define CLK_APMIXED_SGMPLL 3
+#define CLK_APMIXED_WEDMCUPLL 4
+#define CLK_APMIXED_NET1PLL 5
+#define CLK_APMIXED_MPLL 6
+#define CLK_APMIXED_APLL2 7
#define CLK_APMIXED_NR_CLK 8
/* SGMIISYS_0 */
-#define CK_SGM0_TX_EN 0
-#define CK_SGM0_RX_EN 1
-#define CK_SGM0_CK0_EN 2
-#define CK_SGM0_CDR_CK0_EN 3
+#define CLK_SGM0_TX_EN 0
+#define CLK_SGM0_RX_EN 1
+#define CLK_SGM0_CK0_EN 2
+#define CLK_SGM0_CDR_CK0_EN 3
#define CLK_SGMII0_NR_CLK 4
/* SGMIISYS_1 */
-#define CK_SGM1_TX_EN 0
-#define CK_SGM1_RX_EN 1
-#define CK_SGM1_CK1_EN 2
-#define CK_SGM1_CDR_CK1_EN 3
+#define CLK_SGM1_TX_EN 0
+#define CLK_SGM1_RX_EN 1
+#define CLK_SGM1_CK1_EN 2
+#define CLK_SGM1_CDR_CK1_EN 3
#define CLK_SGMII1_NR_CLK 4
/* ETHSYS */
-#define CK_ETH_FE_EN 0
-#define CK_ETH_GP2_EN 1
-#define CK_ETH_GP1_EN 2
-#define CK_ETH_WOCPU0_EN 3
+#define CLK_ETH_FE_EN 0
+#define CLK_ETH_GP2_EN 1
+#define CLK_ETH_GP1_EN 2
+#define CLK_ETH_WOCPU0_EN 3
#define CLK_ETH_NR_CLK 4
#endif /* _DT_BINDINGS_CLK_MT7981_H */
--
2.45.2
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