[PATCH 11/15] clk: mediatek: mt7986: comment out CK_TOP_A_TUNER as not used
Christian Marangi
ansuelsmth at gmail.com
Sat Aug 3 10:40:44 CEST 2024
Comment out CK_TOP_A_TUNER as not used and not defined in upstream
kernel linux. This is to permit support of OF_UPSTREAM and have a 1:1
match with upstream linux clock ID.
Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
drivers/clk/mediatek/clk-mt7986.c | 3 +-
include/dt-bindings/clock/mt7986-clk.h | 122 ++++++++++++-------------
2 files changed, 63 insertions(+), 62 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index d8e0a5790e3..08b7ab8a81e 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -58,7 +58,8 @@ static const struct mtk_fixed_factor top_fixed_divs[] = {
1250),
TOP_FACTOR(CK_TOP_RTC_32P7K, "rtc_32p7k", CK_TOP_XTAL, 1,
1220),
- TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 2, 1),
+ /* Not defined upstream and not used */
+ /* TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 2, 1), */
/* MPLL */
PLL_FACTOR(CK_TOP_MPLL_D2, "mpll_d2", CK_APMIXED_MPLL, 1, 2),
PLL_FACTOR(CK_TOP_MPLL_D4, "mpll_d4", CK_APMIXED_MPLL, 1, 4),
diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h
index 478538d7cce..7df13665900 100644
--- a/include/dt-bindings/clock/mt7986-clk.h
+++ b/include/dt-bindings/clock/mt7986-clk.h
@@ -19,67 +19,67 @@
#define CK_TOP_XTAL_D2 1
#define CK_TOP_RTC_32K 2
#define CK_TOP_RTC_32P7K 3
-#define CK_TOP_A_TUNER 4
-#define CK_TOP_MPLL_D2 5
-#define CK_TOP_MPLL_D4 6
-#define CK_TOP_MPLL_D8 7
-#define CK_TOP_MPLL_D8_D2 8
-#define CK_TOP_MPLL_D3_D2 9
-#define CK_TOP_MMPLL_D2 10
-#define CK_TOP_MMPLL_D4 11
-#define CK_TOP_MMPLL_D8 12
-#define CK_TOP_MMPLL_D8_D2 13
-#define CK_TOP_MMPLL_D3_D8 14
-#define CK_TOP_MMPLL_U2PHYD 15
-#define CK_TOP_APLL2_D4 16
-#define CK_TOP_NET1PLL_D4 17
-#define CK_TOP_NET1PLL_D5 18
-#define CK_TOP_NET1PLL_D5_D2 19
-#define CK_TOP_NET1PLL_D5_D4 20
-#define CK_TOP_NET1PLL_D8_D2 21
-#define CK_TOP_NET1PLL_D8_D4 22
-#define CK_TOP_NET2PLL_D4 23
-#define CK_TOP_NET2PLL_D4_D2 24
-#define CK_TOP_NET2PLL_D3_D2 25
-#define CK_TOP_WEDMCUPLL_D5_D2 26
-#define CK_TOP_NFI1X_SEL 27
-#define CK_TOP_SPINFI_SEL 28
-#define CK_TOP_SPI_SEL 29
-#define CK_TOP_SPIM_MST_SEL 30
-#define CK_TOP_UART_SEL 31
-#define CK_TOP_PWM_SEL 32
-#define CK_TOP_I2C_SEL 33
-#define CK_TOP_PEXTP_TL_SEL 34
-#define CK_TOP_EMMC_250M_SEL 35
-#define CK_TOP_EMMC_416M_SEL 36
-#define CK_TOP_F_26M_ADC_SEL 37
-#define CK_TOP_DRAMC_SEL 38
-#define CK_TOP_DRAMC_MD32_SEL 39
-#define CK_TOP_SYSAXI_SEL 40
-#define CK_TOP_SYSAPB_SEL 41
-#define CK_TOP_ARM_DB_MAIN_SEL 42
-#define CK_TOP_ARM_DB_JTSEL 43
-#define CK_TOP_NETSYS_SEL 44
-#define CK_TOP_NETSYS_500M_SEL 45
-#define CK_TOP_NETSYS_MCU_SEL 46
-#define CK_TOP_NETSYS_2X_SEL 47
-#define CK_TOP_SGM_325M_SEL 48
-#define CK_TOP_SGM_REG_SEL 49
-#define CK_TOP_A1SYS_SEL 50
-#define CK_TOP_CONN_MCUSYS_SEL 51
-#define CK_TOP_EIP_B_SEL 52
-#define CK_TOP_PCIE_PHY_SEL 53
-#define CK_TOP_USB3_PHY_SEL 54
-#define CK_TOP_F26M_SEL 55
-#define CK_TOP_AUD_L_SEL 56
-#define CK_TOP_A_TUNER_SEL 57
-#define CK_TOP_U2U3_SEL 58
-#define CK_TOP_U2U3_SYS_SEL 59
-#define CK_TOP_U2U3_XHCI_SEL 60
-#define CK_TOP_DA_U2_REFSEL 61
-#define CK_TOP_DA_U2_CK_1P_SEL 62
-#define CK_TOP_AP2CNN_HOST_SEL 63
-#define CLK_TOP_NR_CLK 64
+/* #define CK_TOP_A_TUNER 4 */
+#define CK_TOP_MPLL_D2 4
+#define CK_TOP_MPLL_D4 5
+#define CK_TOP_MPLL_D8 6
+#define CK_TOP_MPLL_D8_D2 7
+#define CK_TOP_MPLL_D3_D2 8
+#define CK_TOP_MMPLL_D2 9
+#define CK_TOP_MMPLL_D4 10
+#define CK_TOP_MMPLL_D8 11
+#define CK_TOP_MMPLL_D8_D2 12
+#define CK_TOP_MMPLL_D3_D8 13
+#define CK_TOP_MMPLL_U2PHYD 14
+#define CK_TOP_APLL2_D4 15
+#define CK_TOP_NET1PLL_D4 16
+#define CK_TOP_NET1PLL_D5 17
+#define CK_TOP_NET1PLL_D5_D2 18
+#define CK_TOP_NET1PLL_D5_D4 19
+#define CK_TOP_NET1PLL_D8_D2 20
+#define CK_TOP_NET1PLL_D8_D4 21
+#define CK_TOP_NET2PLL_D4 22
+#define CK_TOP_NET2PLL_D4_D2 23
+#define CK_TOP_NET2PLL_D3_D2 24
+#define CK_TOP_WEDMCUPLL_D5_D2 25
+#define CK_TOP_NFI1X_SEL 26
+#define CK_TOP_SPINFI_SEL 27
+#define CK_TOP_SPI_SEL 28
+#define CK_TOP_SPIM_MST_SEL 29
+#define CK_TOP_UART_SEL 30
+#define CK_TOP_PWM_SEL 31
+#define CK_TOP_I2C_SEL 32
+#define CK_TOP_PEXTP_TL_SEL 33
+#define CK_TOP_EMMC_250M_SEL 34
+#define CK_TOP_EMMC_416M_SEL 35
+#define CK_TOP_F_26M_ADC_SEL 36
+#define CK_TOP_DRAMC_SEL 37
+#define CK_TOP_DRAMC_MD32_SEL 38
+#define CK_TOP_SYSAXI_SEL 39
+#define CK_TOP_SYSAPB_SEL 40
+#define CK_TOP_ARM_DB_MAIN_SEL 41
+#define CK_TOP_ARM_DB_JTSEL 42
+#define CK_TOP_NETSYS_SEL 43
+#define CK_TOP_NETSYS_500M_SEL 44
+#define CK_TOP_NETSYS_MCU_SEL 45
+#define CK_TOP_NETSYS_2X_SEL 46
+#define CK_TOP_SGM_325M_SEL 47
+#define CK_TOP_SGM_REG_SEL 48
+#define CK_TOP_A1SYS_SEL 49
+#define CK_TOP_CONN_MCUSYS_SEL 50
+#define CK_TOP_EIP_B_SEL 51
+#define CK_TOP_PCIE_PHY_SEL 52
+#define CK_TOP_USB3_PHY_SEL 53
+#define CK_TOP_F26M_SEL 54
+#define CK_TOP_AUD_L_SEL 55
+#define CK_TOP_A_TUNER_SEL 56
+#define CK_TOP_U2U3_SEL 57
+#define CK_TOP_U2U3_SYS_SEL 58
+#define CK_TOP_U2U3_XHCI_SEL 59
+#define CK_TOP_DA_U2_REFSEL 60
+#define CK_TOP_DA_U2_CK_1P_SEL 61
+#define CK_TOP_AP2CNN_HOST_SEL 62
+#define CLK_TOP_NR_CLK 63
/*
* INFRACFG_AO
--
2.45.2
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