[PATCH] serial: ns16550: Try get serial clock rate from DT before CLK

[Jonas Karlman]

Initializing a clock driver to read a known static clock rate can take
some time at U-Boot proper pre-reloc phase.

Change to first try and read clock rate from DT to speed up boot time,
fall back to getting the clock rate from clock driver.

This help reduce boot time by around:
- ~35ms on a Radxa ROCK Pi 4 (RK3399)
- ~15ms on a Radxa ZERO 3W (RK3566)
Time that is wasted getting a static rate known at compile time.

Signed-off-by: Jonas Karlman <jonas at kwiboo.se>
---
 drivers/serial/ns16550.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 6fcb5b523acb..07f9ac00e113 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -565,19 +565,19 @@ int ns16550_serial_of_to_plat(struct udevice *dev)
 	plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0);
 	plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1);
 
-	err = clk_get_by_index(dev, 0, &clk);
-	if (!err) {
-		err = clk_get_rate(&clk);
-		if (!IS_ERR_VALUE(err))
-			plat->clock = err;
-	} else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
-		debug("ns16550 failed to get clock\n");
-		return err;
-	}
-
 	if (!plat->clock)
-		plat->clock = dev_read_u32_default(dev, "clock-frequency",
-						   CFG_SYS_NS16550_CLK);
+		plat->clock = dev_read_u32_default(dev, "clock-frequency", 0);
+	if (!plat->clock) {
+		err = clk_get_by_index(dev, 0, &clk);
+		if (!err) {
+			err = clk_get_rate(&clk);
+			if (!IS_ERR_VALUE(err))
+				plat->clock = err;
+		} else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
+			debug("ns16550 failed to get clock\n");
+			return err;
+		}
+	}
 	if (!plat->clock)
 		plat->clock = CFG_SYS_NS16550_CLK;
 	if (!plat->clock) {
-- 
2.45.2