[PATCH] ARM: zynq: Add support for 7z010_lr and 7z020_lr

[Michal Simek]

On 7/30/24 15:50, Michal Simek wrote:
> Add support for *_lr SOCs. Without this change chips are not going to be
> properly identified and bitstream programming won't work.
> 
> Signed-off-by: Michal Simek <michal.simek at amd.com>
> ---
> 
>   arch/arm/mach-zynq/cpu.c | 2 ++
>   include/zynqpl.h         | 6 ++++++
>   2 files changed, 8 insertions(+)
> 
> diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c
> index c75e453d5730..5b6d765099d4 100644
> --- a/arch/arm/mach-zynq/cpu.c
> +++ b/arch/arm/mach-zynq/cpu.c
> @@ -36,9 +36,11 @@ static const struct {
>   } zynq_fpga_descs[] = {
>   	ZYNQ_DESC(7Z007S),
>   	ZYNQ_DESC(7Z010),
> +	ZYNQ_DESC(7Z010_LR),
>   	ZYNQ_DESC(7Z012S),
>   	ZYNQ_DESC(7Z014S),
>   	ZYNQ_DESC(7Z015),
> +	ZYNQ_DESC(7Z020_LR),
>   	ZYNQ_DESC(7Z020),
>   	ZYNQ_DESC(7Z030),
>   	ZYNQ_DESC(7Z035),
> diff --git a/include/zynqpl.h b/include/zynqpl.h
> index d7dc064585ea..08d067d87572 100644
> --- a/include/zynqpl.h
> +++ b/include/zynqpl.h
> @@ -20,9 +20,11 @@ extern struct xilinx_fpga_op zynq_op;
>   
>   #define XILINX_ZYNQ_XC7Z007S	0x3
>   #define XILINX_ZYNQ_XC7Z010	0x2
> +#define XILINX_ZYNQ_XC7Z010_LR	0x4
>   #define XILINX_ZYNQ_XC7Z012S	0x1c
>   #define XILINX_ZYNQ_XC7Z014S	0x8
>   #define XILINX_ZYNQ_XC7Z015	0x1b
> +#define XILINX_ZYNQ_XC7Z020_LR	0x9
>   #define XILINX_ZYNQ_XC7Z020	0x7
>   #define XILINX_ZYNQ_XC7Z030	0xc
>   #define XILINX_ZYNQ_XC7Z035	0x12
> @@ -32,9 +34,11 @@ extern struct xilinx_fpga_op zynq_op;
>   /* Device Image Sizes */
>   #define XILINX_XC7Z007S_SIZE	16669920/8
>   #define XILINX_XC7Z010_SIZE	16669920/8
> +#define XILINX_XC7Z010_LR_SIZE	16669920/8
>   #define XILINX_XC7Z012S_SIZE	28085344/8
>   #define XILINX_XC7Z014S_SIZE	32364512/8
>   #define XILINX_XC7Z015_SIZE	28085344/8
> +#define XILINX_XC7Z020_LR_SIZE	32364512/8
>   #define XILINX_XC7Z020_SIZE	32364512/8
>   #define XILINX_XC7Z030_SIZE	47839328/8
>   #define XILINX_XC7Z035_SIZE	106571232/8
> @@ -44,9 +48,11 @@ extern struct xilinx_fpga_op zynq_op;
>   /* Device Names */
>   #define XILINX_XC7Z007S_NAME	"7z007s"
>   #define XILINX_XC7Z010_NAME	"7z010"
> +#define XILINX_XC7Z010_LR_NAME	"xc7z010_lr"
>   #define XILINX_XC7Z012S_NAME	"7z012s"
>   #define XILINX_XC7Z014S_NAME	"7z014s"
>   #define XILINX_XC7Z015_NAME	"7z015"
> +#define XILINX_XC7Z020_LR_NAME	"xa7z020_lr"
>   #define XILINX_XC7Z020_NAME	"7z020"
>   #define XILINX_XC7Z030_NAME	"7z030"
>   #define XILINX_XC7Z035_NAME	"7z035"

Applied.
M