[PATCH v2 0/2] Risc-V cache operations

[Mayuresh Chitale]

This patchset adds support for using the CBO instructions to perform the
dcache flush/inval operations for the qemu-riscv board when those are
enabled. The CBO instructions are defined in the Risc-V CMO specification
which can be found at the link below:
https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.pdf

Changes in v2:
 - Use cache functions in generic cache code instead of board specific code
 - Print the zicbom init status in case of a failure

Mayuresh Chitale (2):
  riscv: Add support for defining instructions
  riscv: cache: Add CBO instructions

 arch/riscv/Kconfig                |  4 ++
 arch/riscv/include/asm/insn-def.h | 42 ++++++++++++++
 arch/riscv/lib/cache.c            | 96 +++++++++++++++++++++++++++++++
 3 files changed, 142 insertions(+)
 create mode 100644 arch/riscv/include/asm/insn-def.h

-- 
2.34.1