[PATCH 4/5] mtd: spi: renesas: Configure RPC PHY timing registers

[Marek Vasut]

Make sure RPC PHY timing registers are configured before performing
bus access. These registers might have been left unconfigured or may
have been configured by a prior stage bootloader and leaving them
unconfigured or misconfigured would interfere with U-Boot operation.

Set PHYOFFSET1 DDRTMG field to 3 which enables DDR timing adjustment
when SPIDRE or DRDRE = 0 and set PHYOFFSET2 OCTTMG field to 4 which
makes the interface operate in Serial flash or HyperFlash mode.

Signed-off-by: Marek Vasut <marek.vasut+renesas at mailbox.org>
---
Cc: "Cédric Le Goater" <clg at kaod.org>
Cc: Hai Pham <hai.pham.ud at renesas.com>
Cc: Jagan Teki <jagan at amarulasolutions.com>
Cc: Nobuhiro Iwamatsu <iwamatsu at nigauri.org>
Cc: Paul Barker <paul.barker.ct at bp.renesas.com>
Cc: Tom Rini <trini at konsulko.com>
Cc: William Zhang <william.zhang at broadcom.com>
Cc: u-boot at lists.denx.de
---
 drivers/spi/renesas_rpc_spi.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c
index 50890981149..9aab71db1de 100644
--- a/drivers/spi/renesas_rpc_spi.c
+++ b/drivers/spi/renesas_rpc_spi.c
@@ -145,6 +145,12 @@
 #define RPC_PHYCNT_WBUF		BIT(2)
 #define RPC_PHYCNT_MEM(v)	(((v) & 0x3) << 0)
 
+#define RPCIF_PHYOFFSET1	0x0080	/* R/W */
+#define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
+
+#define RPCIF_PHYOFFSET2	0x0084	/* R/W */
+#define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
+
 #define RPC_PHYINT		0x0088	/* R/W */
 #define RPC_PHYINT_RSTEN	BIT(18)
 #define RPC_PHYINT_WPEN		BIT(17)
@@ -227,6 +233,12 @@ static int rpc_spi_claim_bus(struct udevice *dev, bool manual)
 	struct udevice *bus = dev->parent;
 	struct rpc_spi_priv *priv = dev_get_priv(bus);
 
+	setbits_le32(priv->regs + RPCIF_PHYOFFSET1,
+		     RPCIF_PHYOFFSET1_DDRTMG(3));
+	clrsetbits_le32(priv->regs + RPCIF_PHYOFFSET2,
+			RPCIF_PHYOFFSET2_OCTTMG(7),
+			RPCIF_PHYOFFSET2_OCTTMG(4));
+
 	/* NOTE: The 0x260 are undocumented bits, but they must be set. */
 	writel(RPC_PHYCNT_CAL | rpc_spi_get_strobe_delay() | 0x260,
 	       priv->regs + RPC_PHYCNT);
-- 
2.45.2