[PATCH 1/1] sunxi: sun4i: add missing sdelay() to clock_init_safe()

[Ludwig Kormann]

This delay is required after switching the clock source.

See “A20 Reference manual v1.4” Page 50 / section
“1.5.4.16. CPU/AHB/APB0 CLOCK RATIO”: “If the clock
source is changed, at most to wait for 8 present running
clock cycles.”

This is already implemented in clock_set_pll1(), but was
still missing in clock_init_safe().

Signed-off-by: Ludwig Kormann <ludwig.kormann at ict42.de>
---
 arch/arm/mach-sunxi/clock_sun4i.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-sunxi/clock_sun4i.c b/arch/arm/mach-sunxi/clock_sun4i.c
index 8f1d1b65f0..ac3b7a801f 100644
--- a/arch/arm/mach-sunxi/clock_sun4i.c
+++ b/arch/arm/mach-sunxi/clock_sun4i.c
@@ -25,6 +25,7 @@ void clock_init_safe(void)
 	       APB0_DIV_1 << APB0_DIV_SHIFT |
 	       CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
 	       &ccm->cpu_ahb_apb0_cfg);
+	sdelay(20);
 	writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);
 	sdelay(200);
 	writel(AXI_DIV_1 << AXI_DIV_SHIFT |
@@ -32,6 +33,7 @@ void clock_init_safe(void)
 	       APB0_DIV_1 << APB0_DIV_SHIFT |
 	       CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
 	       &ccm->cpu_ahb_apb0_cfg);
+	sdelay(20);
 #ifdef CONFIG_MACH_SUN7I
 	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
 #endif
-- 
2.39.2