[PATCH 2/4] riscv: dts: sophgo: Add clk node
Kongyang Liu
seashell11234455 at gmail.com
Fri Feb 2 10:43:34 CET 2024
Add clk node for cv18xx SoCs according to patch from Linux kernel.
Link: https://lore.kernel.org/all/IA1PR20MB4953355805F79ABDD7FE9129BB6D2@IA1PR20MB4953.namprd20.prod.outlook.com/
Signed-off-by: Kongyang Liu <seashell11234455 at gmail.com>
---
arch/riscv/dts/cv1800b.dtsi | 4 ++++
arch/riscv/dts/cv18xx.dtsi | 6 ++++++
2 files changed, 10 insertions(+)
diff --git a/arch/riscv/dts/cv1800b.dtsi b/arch/riscv/dts/cv1800b.dtsi
index 165e9e320a..baf641829e 100644
--- a/arch/riscv/dts/cv1800b.dtsi
+++ b/arch/riscv/dts/cv1800b.dtsi
@@ -16,3 +16,7 @@
&clint {
compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
};
+
+&clk {
+ compatible = "sophgo,cv1800-clk";
+};
diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi
index 2d6f4a4b1e..6ea1b2784d 100644
--- a/arch/riscv/dts/cv18xx.dtsi
+++ b/arch/riscv/dts/cv18xx.dtsi
@@ -53,6 +53,12 @@
dma-noncoherent;
ranges;
+ clk: clock-controller at 3002000 {
+ reg = <0x03002000 0x1000>;
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
+
gpio0: gpio at 3020000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3020000 0x1000>;
--
2.41.0
More information about the U-Boot
mailing list